| H A D | bnx2x_link.c | 207 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ macro
3307 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_set_aer_mmd()
3705 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_restart_AN_KR()
3760 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_enable_AN_KR()
3821 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_enable_AN_KR()
3891 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_set_10G_KR()
4076 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_set_20G_force_KR2()
4114 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_set_20G_force_KR2()
4603 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_link_reset()
4652 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_set_warpcore_loopback()
4871 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_master_ln()
4889 CL22_WR_OVER_CL45(bp, phy, bnx2x_reset_unicore()
4938 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4945 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4951 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4957 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4978 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
4988 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5002 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5008 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5036 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5053 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5071 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5078 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5084 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5103 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5114 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5136 CL22_WR_OVER_CL45(bp, phy, bnx2x_program_serdes()
5163 CL22_WR_OVER_CL45(bp, phy, bnx2x_program_serdes()
5180 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_brcm_cl37_advertisement()
5184 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_brcm_cl37_advertisement()
5197 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_ieee_aneg_advertisement()
5205 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_ieee_aneg_advertisement()
5226 CL22_WR_OVER_CL45(bp, phy, bnx2x_restart_autoneg()
5241 CL22_WR_OVER_CL45(bp, phy, bnx2x_restart_autoneg()
5268 CL22_WR_OVER_CL45(bp, phy, bnx2x_initialize_sgmii_process()
5309 CL22_WR_OVER_CL45(bp, phy, bnx2x_initialize_sgmii_process()
5446 CL22_WR_OVER_CL45(bp, phy, bnx2x_check_fallback_to_cl37()
5490 CL22_WR_OVER_CL45(bp, phy, bnx2x_check_fallback_to_cl37()
5834 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_gmii_tx_driver()
5897 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_preemphasis()
5905 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_preemphasis()
13579 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_check_kr2_wa()
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