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Searched refs:CACHELINE_BYTES (Results 1 – 4 of 4) sorted by relevance

/linux-4.1.27/arch/powerpc/lib/
Dcopy_32.S68 CACHELINE_BYTES = L1_CACHE_BYTES define
232 addi r3,r3,CACHELINE_BYTES
236 addi r3,r3,CACHELINE_BYTES
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_ringbuffer.c217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
408 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen8_render_ring_flush()
1360 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in pc_render_add_request()
1383 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ in pc_render_add_request()
1385 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1387 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1389 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1391 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
[all …]
Dintel_ringbuffer.h13 #define CACHELINE_BYTES 64 macro
Dintel_lrc.c1292 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen8_emit_flush_render()