| /linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 114 #define EPROM_CMD_RESERVED_MASK BIT5
144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
159 #define RCR_ACRC32 BIT5
196 #define CAM_USEDK BIT5
220 #define SCR_NoSKMC BIT5
237 #define IMR_HCCADOK BIT5
250 #define TPPoll_CQ BIT5
290 #define AcmHw_ViqStatus BIT5
380 #define RRSR_9M BIT5
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| /linux-4.1.27/drivers/scsi/ |
| D | dc395x.h | 70 #define BIT5 0x00000020 macro
133 #define SRB_ERROR BIT5
138 #define RESIDUAL_VALID BIT5
178 #define EN_TAG_QUEUEING BIT5
634 #define LUN_CHECK BIT5
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| /linux-4.1.27/drivers/staging/rtl8188eu/include/ |
| D | rtl8188e_spec.h | 31 #define BIT5 0x00000020 macro
484 #define CmdEEPROM_En BIT5
491 #define GPIOSEL_ENBT BIT5
505 #define HSIMR_SPS_OCP_INT_EN BIT5
512 #define HSISR_SPS_OCP_INT BIT5
545 #define CMD_READ_EFUSE_MAP_ERR BIT5
556 #define RRSR_9M BIT5
584 #define CAM_USEDK BIT5
637 #define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */
700 #define StopHigh BIT5
[all …]
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| D | rtw_sreset.h | 38 #define WIFI_RX_HANG BIT5
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| D | odm_debug.h | 65 #define ODM_COMP_CCK_PD BIT5
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| D | pwrseq.h | 264 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, \
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| D | odm.h | 422 ODM_BB_CCK_PD = BIT5,
468 ODM_RF_RX_B = BIT5,
506 ODM_CLIENT_MODE = BIT5,
520 ODM_WM_AUTO = BIT5,
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| D | Hal8188EPhyCfg.h | 93 WIRELESS_MODE_AUTO = BIT5,
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| D | osdep_service.h | 93 #define BIT5 0x00000020 macro
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| /linux-4.1.27/drivers/staging/rtl8188eu/hal/ |
| D | rtl8188eu_led.c | 39 usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */ in SwLedOn()
63 usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6)); in SwLedOff()
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| D | odm_RTL8188E.c | 64 BIT5|BIT4|BIT3, 0); in dm_trx_hw_antenna_div_init()
169 phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0); in dm_fast_training_init()
208 BIT5|BIT4|BIT3, default_ant); in rtl88eu_dm_update_rx_idle_ant()
217 BIT5|BIT4|BIT3, default_ant); in rtl88eu_dm_update_rx_idle_ant()
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| D | phy.c | 965 usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT5))); in mac_setting_calibration()
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| /linux-4.1.27/drivers/staging/rtl8192u/ |
| D | r8192U_hw.h | 156 #define RCR_ACRC32 BIT5 // Accept CRC32 error packet
188 #define SCR_NoSKMC BIT5 //No Key Search for Multicast
234 #define AcmHw_ViqStatus BIT5
312 #define RRSR_9M BIT5
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| D | r8192U.h | 51 #define BIT5 0x00000020 macro
97 #define COMP_IO BIT5
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/ |
| D | pwrseq.h | 284 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
405 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
641 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
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| /linux-4.1.27/drivers/video/fbdev/via/ |
| D | dvi.c | 76 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
80 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
422 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
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| D | hw.c | 1711 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1717 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2080 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); in viafb_set_dpa_gfx()
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| D | share.h | 33 #define BIT5 0x20 macro
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| D | viafbdev.c | 1127 (viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 | in viafb_dvp0_proc_show()
1169 reg_val << 4, BIT5); in viafb_dvp0_proc_write()
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 53 #define BIT5 0x00000020 macro
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| D | halbtc8821a2ant.h | 32 #define BT_INFO_8821A_2ANT_B_HID BIT5
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| D | halbtc8723b2ant.h | 35 #define BT_INFO_8723B_2ANT_B_HID BIT5
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| D | halbtc8723b1ant.h | 32 #define BT_INFO_8723B_1ANT_B_HID BIT5
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| D | halbtc8192e2ant.h | 32 #define BT_INFO_8192E_2ANT_B_HID BIT5
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| D | halbtc8821a1ant.h | 34 #define BT_INFO_8821A_1ANT_B_HID BIT5
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| D | halbtcoutsrc.h | 106 #define ALGO_TRACE_FW_DETAIL BIT5
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| D | halbtc8723b1ant.c | 884 if ((byte1 & BIT4) && !(byte1 & BIT5)) { in halbtc8723b1ant_set_fw_ps_tdma()
888 real_byte1 |= BIT5; in halbtc8723b1ant_set_fw_ps_tdma()
890 real_byte5 |= BIT5; in halbtc8723b1ant_set_fw_ps_tdma()
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| /linux-4.1.27/include/uapi/linux/ |
| D | synclink.h | 23 #define BIT5 0x0020 macro
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| /linux-4.1.27/drivers/tty/ |
| D | synclinkmp.c | 437 #define PE BIT5
438 #define ABT BIT5
2604 if (timerstatus0 & (BIT5 | BIT4)) in synclinkmp_interrupt()
2608 if (timerstatus1 & (BIT5 | BIT4)) in synclinkmp_interrupt()
4417 case 6: RegValue |= BIT5 + BIT3; break; in async_mode()
4418 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4580 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; in hdlc_mode()
4581 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ in hdlc_mode()
4612 RegValue |= BIT6 + BIT5; in hdlc_mode()
4625 RegValue |= BIT6 + BIT5; in hdlc_mode()
[all …]
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| D | synclink_gt.c | 422 #define IRQ_DCD BIT5
2233 if (status & (BIT5 + BIT4)) { in isr_rdma()
2258 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4172 case 7: val |= BIT5; break; in async_mode()
4173 case 8: val |= BIT5 + BIT4; break; in async_mode()
4212 case 7: val |= BIT5; break; in async_mode()
4213 case 8: val |= BIT5 + BIT4; break; in async_mode()
4336 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4338 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4424 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
[all …]
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| D | synclink.c | 491 #define RECEIVE_STATUS BIT5
507 #define RXSTATUS_BREAK_RECEIVED BIT5
508 #define RXSTATUS_ABORT_RECEIVED BIT5
547 #define TXSTATUS_ABORT_SENT BIT5
568 #define MISCSTATUS_CTS_LATCHED BIT5
593 #define SICR_CTS_ACTIVE BIT5
595 #define SICR_CTS (BIT5|BIT4)
628 #define TXSTATUS_ABORT_SENT BIT5
5927 RegValue |= BIT5; in usc_set_async_mode()
5984 RegValue |= BIT5; in usc_set_async_mode()
[all …]
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| /linux-4.1.27/drivers/char/pcmcia/ |
| D | synclink_cs.c | 680 #define CMD_RXFIFO_READ BIT5
908 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) in rx_ready_async()
3036 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3163 val |= BIT5; in hdlc_mode()
3188 val |= BIT5; in hdlc_mode()
3251 val |= BIT5; in hdlc_mode()
3525 val |= BIT5; in async_mode()
3568 val |= BIT5; in async_mode()
3693 else if (!(status & BIT5)) { in rx_get_frame()
3724 if (status & BIT5) in rx_get_frame()
[all …]
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| /linux-4.1.27/drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 27 #define BIT5 0x00000020 macro
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| D | rtllib.h | 130 #define RT_RF_OFF_LEVL_FW_32K BIT5
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| /linux-4.1.27/drivers/staging/rtl8192u/ieee80211/ |
| D | rtl819x_Qos.h | 9 #define BIT5 0x00000020 macro
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/ |
| D | reg.h | 389 #define RRSR_9M BIT5
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| /linux-4.1.27/drivers/scsi/lpfc/ |
| D | lpfc_hw4.h | 679 #define LPFC_SLI4_INTR5 BIT5
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