| /linux-4.1.27/drivers/staging/emxx_udc/ |
| D | emxx_udc.h | 99 #define BIT12 0x00001000 macro
156 #define UFRAME (BIT14+BIT13+BIT12)
187 #define EP4_INT BIT12
214 #define EP4_EN BIT12
255 #define EP0_OUT_EMPTY BIT12
397 #define MCYCLE_RST BIT12 /* RW */
433 #define DIRPD BIT12 /* RW */
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| /linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
158 #define RCR_AICV BIT12
230 #define IMR_RXFOVW BIT12
257 #define TPPoll_StopVO BIT12
387 #define RRSR_MCS0 BIT12
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| /linux-4.1.27/drivers/staging/rtl8188eu/hal/ |
| D | odm_RTL8188E.c | 92 BIT13|BIT12|BIT11, 2); in dm_trx_hw_antenna_div_init()
139 phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2); in dm_fast_training_init()
147 phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1); in dm_fast_training_init()
212 BIT14|BIT13|BIT12, default_ant); in rtl88eu_dm_update_rx_idle_ant()
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| D | odm.c | 763 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); in odm_FalseAlarmCounterStatistics()
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 60 #define BIT12 0x00001000 macro
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| /linux-4.1.27/drivers/staging/rtl8188eu/include/ |
| D | odm_debug.h | 72 #define ODM_COMP_DYNAMIC_PRICCA BIT12
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| D | osdep_service.h | 100 #define BIT12 0x00001000 macro
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| D | rtl8188e_spec.h | 38 #define BIT12 0x00001000 macro
563 #define RRSR_MCS0 BIT12
630 #define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */
719 #define RCR_ACF BIT12 /* Accept control type frame */
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| D | odm.h | 429 ODM_BB_RXHP = BIT12,
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| /linux-4.1.27/drivers/staging/rtl8192u/ |
| D | r8192U_hw.h | 155 #define RCR_AICV BIT12 // Accept ICV error packet
319 #define RRSR_MCS0 BIT12
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| D | r8192U.h | 58 #define BIT12 0x00001000 macro
106 #define COMP_RATE BIT12 /* Rate Adaptive mechanism */
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| /linux-4.1.27/include/uapi/linux/ |
| D | synclink.h | 30 #define BIT12 0x1000 macro
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| /linux-4.1.27/drivers/scsi/ |
| D | dc395x.h | 63 #define BIT12 0x00001000 macro
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| /linux-4.1.27/drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 34 #define BIT12 0x00001000 macro
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| /linux-4.1.27/drivers/tty/ |
| D | synclink.c | 561 #define MISCSTATUS_TXC BIT12
582 #define SICR_TXC_INACTIVE BIT12
583 #define SICR_TXC (BIT13|BIT12)
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); in shutdown()
4696 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); in usc_set_sdlc_mode()
4730 RegValue |= BIT12; in usc_set_sdlc_mode()
4772 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
5178 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break; in usc_set_sdlc_mode()
6053 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); in usc_set_async_mode()
[all …]
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| D | synclink_gt.c | 414 #define IRQ_TXIDLE BIT12
4319 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()
4320 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4321 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4322 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4392 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()
4393 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4394 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4395 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
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| /linux-4.1.27/drivers/staging/rtl8192u/ieee80211/ |
| D | rtl819x_Qos.h | 16 #define BIT12 0x00001000 macro
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/ |
| D | reg.h | 396 #define RRSR_MCS0 BIT12
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| /linux-4.1.27/drivers/scsi/lpfc/ |
| D | lpfc_hw4.h | 686 #define LPFC_SLI4_INTR12 BIT12
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| /linux-4.1.27/drivers/char/pcmcia/ |
| D | synclink_cs.c | 293 #define IRQ_UNDERRUN BIT12 // transmit data underrun
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