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Searched refs:BIT0 (Results 1 – 49 of 49) sorted by relevance

/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
Dpwrseq.h60 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
203 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
269 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
393 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
411 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
[all …]
/linux-4.1.27/drivers/staging/rtl8188eu/include/
Dpwrseq.h71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, \
86 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, \
140 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
153 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
187 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
216 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
254 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
298 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, \
Drtl8188e_spec.h26 #define BIT0 0x00000001 macro
504 #define HSIMR_GPIO12_0_INT_EN BIT0
511 #define HSISR_GPIO12_0_INT BIT0
540 #define CMD_INIT_LLT BIT0
551 #define RRSR_1M BIT0
574 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
610 #define WOW_PMEN BIT0 /* Power management Enable. */
642 #define IMR_ROK_88E BIT0 /* Receive DMA OK */
705 #define StopVO BIT0
732 #define RCR_AAP BIT0 /* Accept all unicast packet */
[all …]
Drtw_sreset.h33 #define USB_VEN_REQ_CMD_FAIL BIT0
Dodm.h417 ODM_BB_DIG = BIT0,
463 ODM_RF_TX_A = BIT0,
501 ODM_NO_LINK = BIT0,
515 ODM_WM_B = BIT0,
526 ODM_BAND_2_4G = BIT0,
Dodm_reg.h115 #define BIT_FA_RESET BIT0
Dodm_debug.h60 #define ODM_COMP_DIG BIT0
DHal8188EPhyCfg.h91 WIRELESS_MODE_B = BIT0,
Dosdep_service.h88 #define BIT0 0x00000001 macro
Dhal_intf.h28 RTW_PCIE = BIT0,
/linux-4.1.27/drivers/video/fbdev/via/
Ddvi.c59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
377 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
409 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
[all …]
Dlcd.c359 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
577 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
599 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
666 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
675 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
684 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
760 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
859 bdithering = BIT0; in fill_lcd_format()
[all …]
Dvia_utility.c166 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
183 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
221 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
Dhw.c487 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
964 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
1001 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
1002 get_bit = (timing_value & (BIT0 << bit_num)); in viafb_load_reg()
1682 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1696 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
1703 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
Dshare.h28 #define BIT0 0x01 macro
/linux-4.1.27/drivers/scsi/
Ddc395x.h75 #define BIT0 0x00000001 macro
78 #define UNIT_ALLOCATED BIT0
84 #define DASD_SUPPORT BIT0
120 #define RESET_DEV BIT0
125 #define ABORT_DEV_ BIT0
128 #define SRB_OK BIT0
142 #define AUTO_REQSENSE BIT0
173 #define SYNC_NEGO_ENABLE BIT0
629 #define MORE2_DRV BIT0
/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
163 #define RCR_AAP BIT0
215 #define SCR_TxUseDK BIT0
242 #define IMR_ROK BIT0
245 #define TPPoll_BKQ BIT0
285 #define AcmHw_HwEn BIT0
293 #define AcmFw_BeqStatus BIT0
346 #define BW_OPMODE_11J BIT0
375 #define RRSR_1M BIT0
/linux-4.1.27/drivers/staging/rtl8192u/
Dr8192U_hw.h160 #define RCR_AAP BIT0 // Accept all unicast packet
183 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
229 #define AcmHw_HwEn BIT0
284 #define BW_OPMODE_11J BIT0
307 #define RRSR_1M BIT0
Dr8192U.h46 #define BIT0 0x00000001 macro
90 #define COMP_TRACE BIT0 /* Function call tracing. */
Dr8192U_dm.c2381 if (tmp1byte&BIT6 || tmp1byte&BIT0) { in dm_check_pbc_gpio()
/linux-4.1.27/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbtc8723b1ant.h37 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
40 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbtc8821a1ant.h39 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
42 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbt_precomp.h48 #define BIT0 0x00000001 macro
Dhalbtc8821a2ant.c344 h2c_parameter[0] |= BIT0; /* trigger */ in halbtc8821a2ant_query_bt_info()
628 h2c_parameter[1] |= BIT0; in btc8821a2ant_set_fw_bt_lna_constr()
710 h2c_parameter[0] |= BIT0; in halbtc8821a2ant_set_bt_auto_report()
827 h2c_parameter[1] |= BIT0; in btc8821a2ant_SetSwPenTxRateAdapt()
1028 h2c_parameter[0] |= BIT0;/* function enable */ in halbtc8821a2ant_set_fw_ignore_wlan_act()
2573 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_a2dp_pan_hs()
2596 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_a2dp_pan_hs()
2808 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
2818 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
2846 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
[all …]
Dhalbtcoutsrc.h97 #define INTF_INIT BIT0
101 #define ALGO_BT_RSSI_STATE BIT0
113 #define WIFI_STA_CONNECTED BIT0
Dhalbtc8821a2ant.h37 #define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
Dhalbtc8723b2ant.h40 #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
Dhalbtc8192e2ant.h37 #define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
Dhalbtc8821a1ant.c432 h2c_parameter[0] |= BIT0; /* trigger*/ in halbtc8821a1ant_query_bt_info()
671 h2c_parameter[0] |= BIT0; in halbtc8821a1ant_set_bt_auto_report()
713 h2c_parameter[1] |= BIT0; in btc8821a1ant_set_sw_pen_tx_rate()
840 h2c_parameter[0] |= BIT0; /* function enable*/ in btc8821a1ant_set_fw_ignore_wlan_act()
2363 (bt_info_ext&BIT0) ? in ex_halbtc8821a1ant_display_coex_info()
Dhalbtc8723b1ant.c436 h2c_parameter[0] |= BIT0; /* trigger*/ in halbtc8723b1ant_query_bt_info()
712 h2c_parameter[1] |= BIT0; in btc8723b1ant_set_sw_pen_tx_rate_adapt()
840 h2c_parameter[0] |= BIT0; /* function enable */ in halbtc8723b1ant_SetFwIgnoreWlanAct()
2335 if (u32tmp & BIT0) { in halbtc8723b1ant_init_hw_config()
2523 (bt_info_ext & BIT0) ? "Basic rate" : "EDR rate"); in ex_halbtc8723b1ant_display_coex_info()
Dhalbtc8192e2ant.c519 h2c_parameter[0] |= BIT0; /* trigger */ in halbtc8192e2ant_querybt_info()
829 h2c_parameter[0] |= BIT0; in halbtc8192e2ant_set_bt_autoreport()
1137 h2c_parameter[0] |= BIT0; /* function enable */ in halbtc8192e2ant_set_fw_ignore_wlanact()
3276 u8tmp |= BIT0; in halbtc8192e2ant_init_hwconfig()
3280 u8tmp |= BIT0; in halbtc8192e2ant_init_hwconfig()
3407 (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate"); in ex_halbtc8192e2ant_display_coex_info()
Dhalbtc8723b2ant.c312 h2c_parameter[0] |= BIT0; /* trigger */ in btc8723b2ant_query_bt_info()
783 h2c_parameter[1] |= BIT0; in btc8723b_set_penalty_txrate()
1100 h2c_parameter[0] |= BIT0;/* function enable*/ in btc8723b2ant_set_fw_ignore_wlan_act()
3259 (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate"); in ex_btc8723b2ant_display_coex_info()
/linux-4.1.27/drivers/staging/rtl8192e/
Drtl819x_Qos.h22 #define BIT0 0x00000001 macro
234 #define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
235 #define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
Drtllib.h125 #define RT_RF_OFF_LEVL_ASPM BIT0
/linux-4.1.27/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h4 #define BIT0 0x00000001 macro
378 #define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
379 #define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
/linux-4.1.27/drivers/tty/
Dsynclink_gt.c215 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
383 #define MASK_FRAMING BIT0
425 #define IRQ_MASTER BIT0
1882 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1885 else if (status & BIT0) in rx_async()
1892 else if (status & BIT0) in rx_async()
2105 if (status & BIT0) { in ri_change()
3911 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3924 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
[all …]
Dsynclinkmp.c418 #define RXRDYE BIT0
430 #define BRKE BIT0
431 #define IDLD BIT0
2174 while((status = read_reg(info,CST0)) & BIT0) in isr_rxrdy()
2585 if (status & BIT0 << shift) in synclinkmp_interrupt()
2594 if (dmastatus & BIT0 << shift) in synclinkmp_interrupt()
4035 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4038 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); in enable_loopback()
4053 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4423 RegValue |= BIT0; in async_mode()
[all …]
Dsynclink.c496 #define MISC BIT0
515 #define RXSTATUS_DATA_AVAILABLE BIT0
553 #define TXSTATUS_FIFO_EMPTY BIT0
573 #define MISCSTATUS_BRG0_ZERO BIT0
599 #define SICR_BRG0_ZERO BIT0
633 #define TXSTATUS_FIFO_EMPTY BIT0
636 #define DICR_TRANSMIT BIT0
1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 ); in mgsl_isr_transmit_dma()
5249 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5312 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
[all …]
/linux-4.1.27/drivers/staging/rtl8188eu/core/
Drtw_efuse.c399 if (!(word_en&BIT0)) { in Efuse_WordEnableDataWrite()
407 badworden &= (~BIT0); in Efuse_WordEnableDataWrite()
741 if (((pTargetPkt->word_en & BIT0) == 0) && in wordEnMatched()
742 ((pCurPkt->word_en & BIT0) == 0)) in wordEnMatched()
743 match_word_en &= ~BIT0; /* enable word 0 */ in wordEnMatched()
/linux-4.1.27/drivers/staging/rtl8188eu/hal/
Dodm_HWConfig.c365 pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; in odm_Process_RSSIForDM()
394 OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0; in odm_Process_RSSIForDM()
Dodm_RTL8188E.c173 phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); in dm_fast_training_init()
234 dm_fat_tbl->antsel_a[mac_id] = target_ant&BIT0; in update_tx_ant_88eu()
Dusb_halinit.c811 usb_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0)); in rtl8188eu_hal_init()
950 usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT0)); in CardDisableRTL8188EU()
1180 haldata->RegReg542 |= BIT0; in ResumeTxBeacon()
1194 haldata->RegReg542 &= ~(BIT0); in StopTxBeacon()
1801 usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT0); in SetHwReg8188EU()
1821 val[0] = (BIT0 & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false; in GetHwReg8188EU()
Drtl8188e_cmd.c601 haldata->RegCR_1 |= BIT0; in rtl8188e_set_FwJoinBssReport_cmd()
671 haldata->RegCR_1 &= (~BIT0); in rtl8188e_set_FwJoinBssReport_cmd()
Dbb_cfg.c716 usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1)); in rtl88eu_phy_bb_config()
/linux-4.1.27/include/uapi/linux/
Dsynclink.h18 #define BIT0 0x0001 macro
/linux-4.1.27/drivers/net/ethernet/cirrus/
Dcs89x0.h463 #define BIT0 1 macro
/linux-4.1.27/drivers/char/pcmcia/
Dsynclink_cs.c303 #define IRQ_RXFIFO BIT0 // receive pool full
311 #define PVR_DTR BIT0
684 #define CMD_TXRESET BIT0 // transmit reset
1185 if (gis & (BIT1 | BIT0)) { in mgslpc_isr()
3032 val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); in loopback_enable()
3046 val = read_reg(info, CHA + MODE) | BIT0; in loopback_enable()
3099 val |= BIT0; in hdlc_mode()
3169 val |= BIT0; in hdlc_mode()
3445 val |= BIT0; in async_mode()
3523 val |= BIT0; /* 7 bits */ in async_mode()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/
Dreg.h384 #define RRSR_1M BIT0
519 #define WOW_PMEN BIT0 /* Power management Enable. */
/linux-4.1.27/drivers/scsi/lpfc/
Dlpfc_hw4.h674 #define LPFC_SLI4_INTR0 BIT0