Searched refs:BAR (Results 1 – 20 of 20) sorted by relevance
162 discover the BAR sizes and assign addresses for them. For VF devices,163 software uses VF BAR registers in the *PF* SR-IOV Capability to167 When a VF BAR in the PF SR-IOV Capability is programmed, it sets the170 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.172 is a BAR0 for one of the VFs. Note that even though the VF BAR185 the segment size matches the smallest VF BAR, which means larger VF200 and different segment sizes. If we have VFs that each have a 1MB BAR201 and a 32MB BAR, we could use one M64 window to assign 1MB segments and205 more in the next two sections. For a given VF BAR, we need to206 effectively reserve the entire 256 segments (256 * VF BAR size) and[all …]
95 config space (the base address registers (BAR's), latency timer,174 It saves the device BAR's and then calls rpaphp_unconfig_pci_adapter().180 It then resets the PCI card, reconfigures the device BAR's, and
43 .handle = NV_SUBDEV(BAR, 0xea),
212 .handle = NV_SUBDEV(BAR, 0xc0),
264 .handle = NV_SUBDEV(BAR, 0x50),
21 offset from be base of the BAR (which would be23 the same BAR)
91 bool "foo" if BAR92 default y if BAR94 depends on BAR110 if FOO depends on BAR that is not set.393 depends on BAR && m
309 BAR, DCCR, BRP, USP enumerator
37 - Get both the BAR cookies used by CPU and actual PCI BAR 40 BAR values to destination address to make decision.44 PCI BAR value from the BAR cookie is now useless.
10 - Get both the BAR cookies actual and PCI BAR values.
29 Capabilities: [58] Debug port: BAR=1 offset=00a0
79 To access PCI via this space, we simply ioremap() the BAR
206 To access PCI via this space, we simply ioremap() the BAR
284 pcim_iomap_table() : array of mapped addresses indexed by BAR
66 example, if a PCI device has a BAR, the kernel reads the bus address (A)67 from the BAR and converts it to a CPU physical address (B). The address B897 ringp->len = BAR;902 dma_unmap_len_set(ringp, len, BAR);
450 The MSI-X capability specifies a BAR and offset within that BAR for the
268 restoring the PCI BAR's and PCI configuration header to a state
662 39 SPACE BAR
353 #define BAR 0x80 macro
1310 Only PCI header type 0 devices with PCI BAR resources are supported by