| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/mfd/ |
| H A D | dbx500-prcmu.h | 12 #define ARMCLK 0 macro
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| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/mfd/ |
| H A D | dbx500-prcmu.h | 12 #define ARMCLK 0 macro
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| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/mfd/ |
| H A D | dbx500-prcmu.h | 12 #define ARMCLK 0 macro
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| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/mfd/ |
| H A D | dbx500-prcmu.h | 12 #define ARMCLK 0 macro
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| /linux-4.1.27/arch/arm/plat-samsung/include/plat/ |
| H A D | cpu-freq.h | 23 * @armclk: The ARMCLK frequency in Hz.
76 * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
77 * @dvs: Non-zero if using DVS mode for ARMCLK.
115 * Registration depends on the driver being used, the ARMCLK only
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| H A D | cpu-freq-core.h | 142 * ARMCLK.
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| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/mfd/ |
| H A D | dbx500-prcmu.h | 12 #define ARMCLK 0 macro
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| /linux-4.1.27/include/dt-bindings/mfd/ |
| H A D | dbx500-prcmu.h | 12 #define ARMCLK 0 macro
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| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 31 #define ARMCLK 8 macro
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| H A D | s3c2412.h | 33 #define ARMCLK 10 macro
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| H A D | s3c2443.h | 26 #define ARMCLK 4 macro
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| H A D | samsung,s3c64xx-clock.h | 28 #define ARMCLK 6 macro
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| H A D | rk3188-cru-common.h | 23 #define ARMCLK 7 macro
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| H A D | rk3288-cru.h | 22 #define ARMCLK 6 macro
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| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 31 #define ARMCLK 8 macro
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| H A D | s3c2412.h | 33 #define ARMCLK 10 macro
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| H A D | s3c2443.h | 26 #define ARMCLK 4 macro
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| H A D | samsung,s3c64xx-clock.h | 28 #define ARMCLK 6 macro
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| H A D | rk3188-cru-common.h | 23 #define ARMCLK 7 macro
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| H A D | rk3288-cru.h | 22 #define ARMCLK 6 macro
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| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 31 #define ARMCLK 8 macro
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| H A D | s3c2412.h | 33 #define ARMCLK 10 macro
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| H A D | s3c2443.h | 26 #define ARMCLK 4 macro
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| H A D | samsung,s3c64xx-clock.h | 28 #define ARMCLK 6 macro
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| H A D | rk3188-cru-common.h | 23 #define ARMCLK 7 macro
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| H A D | rk3288-cru.h | 22 #define ARMCLK 6 macro
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| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 31 #define ARMCLK 8 macro
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| H A D | s3c2412.h | 33 #define ARMCLK 10 macro
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| H A D | s3c2443.h | 26 #define ARMCLK 4 macro
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| H A D | samsung,s3c64xx-clock.h | 28 #define ARMCLK 6 macro
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| H A D | rk3188-cru-common.h | 23 #define ARMCLK 7 macro
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| H A D | rk3288-cru.h | 22 #define ARMCLK 6 macro
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| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 31 #define ARMCLK 8 macro
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| H A D | s3c2412.h | 33 #define ARMCLK 10 macro
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| H A D | s3c2443.h | 26 #define ARMCLK 4 macro
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| H A D | samsung,s3c64xx-clock.h | 28 #define ARMCLK 6 macro
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| H A D | rk3188-cru-common.h | 23 #define ARMCLK 7 macro
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| H A D | rk3288-cru.h | 22 #define ARMCLK 6 macro
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| /linux-4.1.27/include/dt-bindings/clock/ |
| H A D | s3c2410.h | 31 #define ARMCLK 8 macro
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| H A D | s3c2412.h | 33 #define ARMCLK 10 macro
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| H A D | s3c2443.h | 26 #define ARMCLK 4 macro
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| H A D | samsung,s3c64xx-clock.h | 28 #define ARMCLK 6 macro
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| H A D | rk3188-cru-common.h | 23 #define ARMCLK 7 macro
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| H A D | rk3288-cru.h | 22 #define ARMCLK 6 macro
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| /linux-4.1.27/drivers/clk/samsung/ |
| H A D | clk-s3c2410.c | 150 ALIAS(ARMCLK, NULL, "armclk"),
214 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
276 MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
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| H A D | clk-s3c2412.c | 145 MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
203 ALIAS(ARMCLK, NULL, "armclk"),
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| H A D | clk-s3c64xx.c | 252 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
257 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
387 ALIAS(ARMCLK, NULL, "armclk"),
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| H A D | clk-s3c2443.c | 123 MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"),
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| /linux-4.1.27/drivers/cpufreq/ |
| H A D | exynos4210-cpufreq.c | 87 /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ exynos4210_set_apll()
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| H A D | exynos4x12-cpufreq.c | 132 /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ exynos4x12_set_apll()
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| H A D | exynos5250-cpufreq.c | 111 /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ set_apll()
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| H A D | s3c24xx-cpufreq-debugfs.c | 91 seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk); info_show()
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| H A D | s3c64xx-cpufreq.c | 163 pr_err("Unable to obtain ARMCLK: %ld\n", s3c64xx_cpufreq_driver_init()
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| H A D | s3c2416-cpufreq.c | 59 /* Sources for the ARMCLK */
411 pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret); s3c2416_cpufreq_driver_init()
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| H A D | s3c2440-cpufreq.c | 73 /* if we are in DVS, we need HCLK to be <= ARMCLK */ s3c2440_cpufreq_calcdivs()
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| /linux-4.1.27/arch/arm/mach-s3c24xx/ |
| H A D | mach-osiris-dvs.c | 48 /* at the moment, we assume ARMCLK = HCLK => DVS */ is_dvs()
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| /linux-4.1.27/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 759 rockchip_clk_register_armclk(ARMCLK, "armclk", rk3066a_clk_init()
778 rockchip_clk_register_armclk(ARMCLK, "armclk", rk3188a_clk_init()
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| H A D | clk-rk3288.c | 899 rockchip_clk_register_armclk(ARMCLK, "armclk", rk3288_clk_init()
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