Searched refs:ARC_REG_TLBPD0 (Results 1 – 3 of 3) sorted by relevance
112 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()120 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()227 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()703 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()
234 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid237 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
22 #define ARC_REG_TLBPD0 0x405 macro