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Searched refs:ARC_REG_TLBPD0 (Results 1 – 3 of 3) sorted by relevance

/linux-4.1.27/arch/arc/mm/
Dtlb.c112 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
120 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()
227 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()
703 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()
Dtlbex.S234 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
237 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
/linux-4.1.27/arch/arc/include/asm/
Dmmu.h22 #define ARC_REG_TLBPD0 0x405 macro