1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
28 *
29 */
30
31 /**
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
33 *
34 * Motivation:
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
38 *
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
42 *
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
47 *
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
55 *
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
58 *
59 * LRC implementation:
60 * Regarding the creation of contexts, we have:
61 *
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
65 *
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
69 *
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
72 *
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
77 * contexts:
78 *
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
83 * so on.
84 *
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
88 *
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
93 *
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
101 * context itself.
102 *
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
108 *
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
114 *
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
122 *
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
132 *
133 */
134
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
142
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
149
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
156
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
185
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
191 enum {
192 ADVANCED_CONTEXT = 0,
193 LEGACY_CONTEXT,
194 ADVANCED_AD_CONTEXT,
195 LEGACY_64B_CONTEXT
196 };
197 #define GEN8_CTX_MODE_SHIFT 3
198 enum {
199 FAULT_AND_HANG = 0,
200 FAULT_AND_HALT, /* Debug only */
201 FAULT_AND_STREAM,
202 FAULT_AND_CONTINUE /* Unsupported */
203 };
204 #define GEN8_CTX_ID_SHIFT 32
205
206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
207 struct intel_context *ctx);
208
209 /**
210 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
211 * @dev: DRM device.
212 * @enable_execlists: value of i915.enable_execlists module parameter.
213 *
214 * Only certain platforms support Execlists (the prerequisites being
215 * support for Logical Ring Contexts and Aliasing PPGTT or better).
216 *
217 * Return: 1 if Execlists is supported and has to be enabled.
218 */
intel_sanitize_enable_execlists(struct drm_device * dev,int enable_execlists)219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
220 {
221 WARN_ON(i915.enable_ppgtt == -1);
222
223 if (INTEL_INFO(dev)->gen >= 9)
224 return 1;
225
226 if (enable_execlists == 0)
227 return 0;
228
229 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
230 i915.use_mmio_flip >= 0)
231 return 1;
232
233 return 0;
234 }
235
236 /**
237 * intel_execlists_ctx_id() - get the Execlists Context ID
238 * @ctx_obj: Logical Ring Context backing object.
239 *
240 * Do not confuse with ctx->id! Unfortunately we have a name overload
241 * here: the old context ID we pass to userspace as a handler so that
242 * they can refer to a context, and the new context ID we pass to the
243 * ELSP so that the GPU can inform us of the context status via
244 * interrupts.
245 *
246 * Return: 20-bits globally unique context ID.
247 */
intel_execlists_ctx_id(struct drm_i915_gem_object * ctx_obj)248 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
249 {
250 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
251
252 /* LRCA is required to be 4K aligned so the more significant 20 bits
253 * are globally unique */
254 return lrca >> 12;
255 }
256
execlists_ctx_descriptor(struct intel_engine_cs * ring,struct drm_i915_gem_object * ctx_obj)257 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
258 struct drm_i915_gem_object *ctx_obj)
259 {
260 struct drm_device *dev = ring->dev;
261 uint64_t desc;
262 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
263
264 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
265
266 desc = GEN8_CTX_VALID;
267 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
268 desc |= GEN8_CTX_L3LLC_COHERENT;
269 desc |= GEN8_CTX_PRIVILEGE;
270 desc |= lrca;
271 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
272
273 /* TODO: WaDisableLiteRestore when we start using semaphore
274 * signalling between Command Streamers */
275 /* desc |= GEN8_CTX_FORCE_RESTORE; */
276
277 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
278 if (IS_GEN9(dev) &&
279 INTEL_REVID(dev) <= SKL_REVID_B0 &&
280 (ring->id == BCS || ring->id == VCS ||
281 ring->id == VECS || ring->id == VCS2))
282 desc |= GEN8_CTX_FORCE_RESTORE;
283
284 return desc;
285 }
286
execlists_elsp_write(struct intel_engine_cs * ring,struct drm_i915_gem_object * ctx_obj0,struct drm_i915_gem_object * ctx_obj1)287 static void execlists_elsp_write(struct intel_engine_cs *ring,
288 struct drm_i915_gem_object *ctx_obj0,
289 struct drm_i915_gem_object *ctx_obj1)
290 {
291 struct drm_device *dev = ring->dev;
292 struct drm_i915_private *dev_priv = dev->dev_private;
293 uint64_t temp = 0;
294 uint32_t desc[4];
295
296 /* XXX: You must always write both descriptors in the order below. */
297 if (ctx_obj1)
298 temp = execlists_ctx_descriptor(ring, ctx_obj1);
299 else
300 temp = 0;
301 desc[1] = (u32)(temp >> 32);
302 desc[0] = (u32)temp;
303
304 temp = execlists_ctx_descriptor(ring, ctx_obj0);
305 desc[3] = (u32)(temp >> 32);
306 desc[2] = (u32)temp;
307
308 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
309 I915_WRITE(RING_ELSP(ring), desc[1]);
310 I915_WRITE(RING_ELSP(ring), desc[0]);
311 I915_WRITE(RING_ELSP(ring), desc[3]);
312
313 /* The context is automatically loaded after the following */
314 I915_WRITE(RING_ELSP(ring), desc[2]);
315
316 /* ELSP is a wo register, so use another nearby reg for posting instead */
317 POSTING_READ(RING_EXECLIST_STATUS(ring));
318 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
319 }
320
execlists_update_context(struct drm_i915_gem_object * ctx_obj,struct drm_i915_gem_object * ring_obj,u32 tail)321 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
322 struct drm_i915_gem_object *ring_obj,
323 u32 tail)
324 {
325 struct page *page;
326 uint32_t *reg_state;
327
328 page = i915_gem_object_get_page(ctx_obj, 1);
329 reg_state = kmap_atomic(page);
330
331 reg_state[CTX_RING_TAIL+1] = tail;
332 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
333
334 kunmap_atomic(reg_state);
335
336 return 0;
337 }
338
execlists_submit_contexts(struct intel_engine_cs * ring,struct intel_context * to0,u32 tail0,struct intel_context * to1,u32 tail1)339 static void execlists_submit_contexts(struct intel_engine_cs *ring,
340 struct intel_context *to0, u32 tail0,
341 struct intel_context *to1, u32 tail1)
342 {
343 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
344 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
345 struct drm_i915_gem_object *ctx_obj1 = NULL;
346 struct intel_ringbuffer *ringbuf1 = NULL;
347
348 BUG_ON(!ctx_obj0);
349 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
350 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
351
352 execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
353
354 if (to1) {
355 ringbuf1 = to1->engine[ring->id].ringbuf;
356 ctx_obj1 = to1->engine[ring->id].state;
357 BUG_ON(!ctx_obj1);
358 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
359 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
360
361 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
362 }
363
364 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
365 }
366
execlists_context_unqueue(struct intel_engine_cs * ring)367 static void execlists_context_unqueue(struct intel_engine_cs *ring)
368 {
369 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
370 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
371
372 assert_spin_locked(&ring->execlist_lock);
373
374 if (list_empty(&ring->execlist_queue))
375 return;
376
377 /* Try to read in pairs */
378 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
379 execlist_link) {
380 if (!req0) {
381 req0 = cursor;
382 } else if (req0->ctx == cursor->ctx) {
383 /* Same ctx: ignore first request, as second request
384 * will update tail past first request's workload */
385 cursor->elsp_submitted = req0->elsp_submitted;
386 list_del(&req0->execlist_link);
387 list_add_tail(&req0->execlist_link,
388 &ring->execlist_retired_req_list);
389 req0 = cursor;
390 } else {
391 req1 = cursor;
392 break;
393 }
394 }
395
396 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
397 /*
398 * WaIdleLiteRestore: make sure we never cause a lite
399 * restore with HEAD==TAIL
400 */
401 if (req0 && req0->elsp_submitted) {
402 /*
403 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
404 * as we resubmit the request. See gen8_emit_request()
405 * for where we prepare the padding after the end of the
406 * request.
407 */
408 struct intel_ringbuffer *ringbuf;
409
410 ringbuf = req0->ctx->engine[ring->id].ringbuf;
411 req0->tail += 8;
412 req0->tail &= ringbuf->size - 1;
413 }
414 }
415
416 WARN_ON(req1 && req1->elsp_submitted);
417
418 execlists_submit_contexts(ring, req0->ctx, req0->tail,
419 req1 ? req1->ctx : NULL,
420 req1 ? req1->tail : 0);
421
422 req0->elsp_submitted++;
423 if (req1)
424 req1->elsp_submitted++;
425 }
426
execlists_check_remove_request(struct intel_engine_cs * ring,u32 request_id)427 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
428 u32 request_id)
429 {
430 struct drm_i915_gem_request *head_req;
431
432 assert_spin_locked(&ring->execlist_lock);
433
434 head_req = list_first_entry_or_null(&ring->execlist_queue,
435 struct drm_i915_gem_request,
436 execlist_link);
437
438 if (head_req != NULL) {
439 struct drm_i915_gem_object *ctx_obj =
440 head_req->ctx->engine[ring->id].state;
441 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
442 WARN(head_req->elsp_submitted == 0,
443 "Never submitted head request\n");
444
445 if (--head_req->elsp_submitted <= 0) {
446 list_del(&head_req->execlist_link);
447 list_add_tail(&head_req->execlist_link,
448 &ring->execlist_retired_req_list);
449 return true;
450 }
451 }
452 }
453
454 return false;
455 }
456
457 /**
458 * intel_lrc_irq_handler() - handle Context Switch interrupts
459 * @ring: Engine Command Streamer to handle.
460 *
461 * Check the unread Context Status Buffers and manage the submission of new
462 * contexts to the ELSP accordingly.
463 */
intel_lrc_irq_handler(struct intel_engine_cs * ring)464 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
465 {
466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
467 u32 status_pointer;
468 u8 read_pointer;
469 u8 write_pointer;
470 u32 status;
471 u32 status_id;
472 u32 submit_contexts = 0;
473
474 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
475
476 read_pointer = ring->next_context_status_buffer;
477 write_pointer = status_pointer & 0x07;
478 if (read_pointer > write_pointer)
479 write_pointer += 6;
480
481 spin_lock(&ring->execlist_lock);
482
483 while (read_pointer < write_pointer) {
484 read_pointer++;
485 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
486 (read_pointer % 6) * 8);
487 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
488 (read_pointer % 6) * 8 + 4);
489
490 if (status & GEN8_CTX_STATUS_PREEMPTED) {
491 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
492 if (execlists_check_remove_request(ring, status_id))
493 WARN(1, "Lite Restored request removed from queue\n");
494 } else
495 WARN(1, "Preemption without Lite Restore\n");
496 }
497
498 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
499 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
500 if (execlists_check_remove_request(ring, status_id))
501 submit_contexts++;
502 }
503 }
504
505 if (submit_contexts != 0)
506 execlists_context_unqueue(ring);
507
508 spin_unlock(&ring->execlist_lock);
509
510 WARN(submit_contexts > 2, "More than two context complete events?\n");
511 ring->next_context_status_buffer = write_pointer % 6;
512
513 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
514 ((u32)ring->next_context_status_buffer & 0x07) << 8);
515 }
516
execlists_context_queue(struct intel_engine_cs * ring,struct intel_context * to,u32 tail,struct drm_i915_gem_request * request)517 static int execlists_context_queue(struct intel_engine_cs *ring,
518 struct intel_context *to,
519 u32 tail,
520 struct drm_i915_gem_request *request)
521 {
522 struct drm_i915_gem_request *cursor;
523 struct drm_i915_private *dev_priv = ring->dev->dev_private;
524 unsigned long flags;
525 int num_elements = 0;
526
527 if (to != ring->default_context)
528 intel_lr_context_pin(ring, to);
529
530 if (!request) {
531 /*
532 * If there isn't a request associated with this submission,
533 * create one as a temporary holder.
534 */
535 request = kzalloc(sizeof(*request), GFP_KERNEL);
536 if (request == NULL)
537 return -ENOMEM;
538 request->ring = ring;
539 request->ctx = to;
540 kref_init(&request->ref);
541 request->uniq = dev_priv->request_uniq++;
542 i915_gem_context_reference(request->ctx);
543 } else {
544 i915_gem_request_reference(request);
545 WARN_ON(to != request->ctx);
546 }
547 request->tail = tail;
548
549 intel_runtime_pm_get(dev_priv);
550
551 spin_lock_irqsave(&ring->execlist_lock, flags);
552
553 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
554 if (++num_elements > 2)
555 break;
556
557 if (num_elements > 2) {
558 struct drm_i915_gem_request *tail_req;
559
560 tail_req = list_last_entry(&ring->execlist_queue,
561 struct drm_i915_gem_request,
562 execlist_link);
563
564 if (to == tail_req->ctx) {
565 WARN(tail_req->elsp_submitted != 0,
566 "More than 2 already-submitted reqs queued\n");
567 list_del(&tail_req->execlist_link);
568 list_add_tail(&tail_req->execlist_link,
569 &ring->execlist_retired_req_list);
570 }
571 }
572
573 list_add_tail(&request->execlist_link, &ring->execlist_queue);
574 if (num_elements == 0)
575 execlists_context_unqueue(ring);
576
577 spin_unlock_irqrestore(&ring->execlist_lock, flags);
578
579 return 0;
580 }
581
logical_ring_invalidate_all_caches(struct intel_ringbuffer * ringbuf,struct intel_context * ctx)582 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
583 struct intel_context *ctx)
584 {
585 struct intel_engine_cs *ring = ringbuf->ring;
586 uint32_t flush_domains;
587 int ret;
588
589 flush_domains = 0;
590 if (ring->gpu_caches_dirty)
591 flush_domains = I915_GEM_GPU_DOMAINS;
592
593 ret = ring->emit_flush(ringbuf, ctx,
594 I915_GEM_GPU_DOMAINS, flush_domains);
595 if (ret)
596 return ret;
597
598 ring->gpu_caches_dirty = false;
599 return 0;
600 }
601
execlists_move_to_gpu(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,struct list_head * vmas)602 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
603 struct intel_context *ctx,
604 struct list_head *vmas)
605 {
606 struct intel_engine_cs *ring = ringbuf->ring;
607 struct i915_vma *vma;
608 uint32_t flush_domains = 0;
609 bool flush_chipset = false;
610 int ret;
611
612 list_for_each_entry(vma, vmas, exec_list) {
613 struct drm_i915_gem_object *obj = vma->obj;
614
615 ret = i915_gem_object_sync(obj, ring);
616 if (ret)
617 return ret;
618
619 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
620 flush_chipset |= i915_gem_clflush_object(obj, false);
621
622 flush_domains |= obj->base.write_domain;
623 }
624
625 if (flush_domains & I915_GEM_DOMAIN_GTT)
626 wmb();
627
628 /* Unconditionally invalidate gpu caches and ensure that we do flush
629 * any residual writes from the previous batch.
630 */
631 return logical_ring_invalidate_all_caches(ringbuf, ctx);
632 }
633
634 /**
635 * execlists_submission() - submit a batchbuffer for execution, Execlists style
636 * @dev: DRM device.
637 * @file: DRM file.
638 * @ring: Engine Command Streamer to submit to.
639 * @ctx: Context to employ for this submission.
640 * @args: execbuffer call arguments.
641 * @vmas: list of vmas.
642 * @batch_obj: the batchbuffer to submit.
643 * @exec_start: batchbuffer start virtual address pointer.
644 * @dispatch_flags: translated execbuffer call flags.
645 *
646 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
647 * away the submission details of the execbuffer ioctl call.
648 *
649 * Return: non-zero if the submission fails.
650 */
intel_execlists_submission(struct drm_device * dev,struct drm_file * file,struct intel_engine_cs * ring,struct intel_context * ctx,struct drm_i915_gem_execbuffer2 * args,struct list_head * vmas,struct drm_i915_gem_object * batch_obj,u64 exec_start,u32 dispatch_flags)651 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
652 struct intel_engine_cs *ring,
653 struct intel_context *ctx,
654 struct drm_i915_gem_execbuffer2 *args,
655 struct list_head *vmas,
656 struct drm_i915_gem_object *batch_obj,
657 u64 exec_start, u32 dispatch_flags)
658 {
659 struct drm_i915_private *dev_priv = dev->dev_private;
660 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
661 int instp_mode;
662 u32 instp_mask;
663 int ret;
664
665 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
666 instp_mask = I915_EXEC_CONSTANTS_MASK;
667 switch (instp_mode) {
668 case I915_EXEC_CONSTANTS_REL_GENERAL:
669 case I915_EXEC_CONSTANTS_ABSOLUTE:
670 case I915_EXEC_CONSTANTS_REL_SURFACE:
671 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
672 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
673 return -EINVAL;
674 }
675
676 if (instp_mode != dev_priv->relative_constants_mode) {
677 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
678 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
679 return -EINVAL;
680 }
681
682 /* The HW changed the meaning on this bit on gen6 */
683 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
684 }
685 break;
686 default:
687 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
688 return -EINVAL;
689 }
690
691 if (args->num_cliprects != 0) {
692 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
693 return -EINVAL;
694 } else {
695 if (args->DR4 == 0xffffffff) {
696 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
697 args->DR4 = 0;
698 }
699
700 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
701 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
702 return -EINVAL;
703 }
704 }
705
706 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
707 DRM_DEBUG("sol reset is gen7 only\n");
708 return -EINVAL;
709 }
710
711 ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
712 if (ret)
713 return ret;
714
715 if (ring == &dev_priv->ring[RCS] &&
716 instp_mode != dev_priv->relative_constants_mode) {
717 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
718 if (ret)
719 return ret;
720
721 intel_logical_ring_emit(ringbuf, MI_NOOP);
722 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
723 intel_logical_ring_emit(ringbuf, INSTPM);
724 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
725 intel_logical_ring_advance(ringbuf);
726
727 dev_priv->relative_constants_mode = instp_mode;
728 }
729
730 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags);
731 if (ret)
732 return ret;
733
734 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
735
736 i915_gem_execbuffer_move_to_active(vmas, ring);
737 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
738
739 return 0;
740 }
741
intel_execlists_retire_requests(struct intel_engine_cs * ring)742 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
743 {
744 struct drm_i915_gem_request *req, *tmp;
745 struct drm_i915_private *dev_priv = ring->dev->dev_private;
746 unsigned long flags;
747 struct list_head retired_list;
748
749 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
750 if (list_empty(&ring->execlist_retired_req_list))
751 return;
752
753 INIT_LIST_HEAD(&retired_list);
754 spin_lock_irqsave(&ring->execlist_lock, flags);
755 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
756 spin_unlock_irqrestore(&ring->execlist_lock, flags);
757
758 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
759 struct intel_context *ctx = req->ctx;
760 struct drm_i915_gem_object *ctx_obj =
761 ctx->engine[ring->id].state;
762
763 if (ctx_obj && (ctx != ring->default_context))
764 intel_lr_context_unpin(ring, ctx);
765 intel_runtime_pm_put(dev_priv);
766 list_del(&req->execlist_link);
767 i915_gem_request_unreference(req);
768 }
769 }
770
intel_logical_ring_stop(struct intel_engine_cs * ring)771 void intel_logical_ring_stop(struct intel_engine_cs *ring)
772 {
773 struct drm_i915_private *dev_priv = ring->dev->dev_private;
774 int ret;
775
776 if (!intel_ring_initialized(ring))
777 return;
778
779 ret = intel_ring_idle(ring);
780 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
781 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
782 ring->name, ret);
783
784 /* TODO: Is this correct with Execlists enabled? */
785 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
786 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
787 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
788 return;
789 }
790 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
791 }
792
logical_ring_flush_all_caches(struct intel_ringbuffer * ringbuf,struct intel_context * ctx)793 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
794 struct intel_context *ctx)
795 {
796 struct intel_engine_cs *ring = ringbuf->ring;
797 int ret;
798
799 if (!ring->gpu_caches_dirty)
800 return 0;
801
802 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
803 if (ret)
804 return ret;
805
806 ring->gpu_caches_dirty = false;
807 return 0;
808 }
809
810 /*
811 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
812 * @ringbuf: Logical Ringbuffer to advance.
813 *
814 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
815 * really happens during submission is that the context and current tail will be placed
816 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
817 * point, the tail *inside* the context is updated and the ELSP written to.
818 */
819 static void
intel_logical_ring_advance_and_submit(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,struct drm_i915_gem_request * request)820 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
821 struct intel_context *ctx,
822 struct drm_i915_gem_request *request)
823 {
824 struct intel_engine_cs *ring = ringbuf->ring;
825
826 intel_logical_ring_advance(ringbuf);
827
828 if (intel_ring_stopped(ring))
829 return;
830
831 execlists_context_queue(ring, ctx, ringbuf->tail, request);
832 }
833
intel_lr_context_pin(struct intel_engine_cs * ring,struct intel_context * ctx)834 static int intel_lr_context_pin(struct intel_engine_cs *ring,
835 struct intel_context *ctx)
836 {
837 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
838 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
839 int ret = 0;
840
841 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
842 if (ctx->engine[ring->id].pin_count++ == 0) {
843 ret = i915_gem_obj_ggtt_pin(ctx_obj,
844 GEN8_LR_CONTEXT_ALIGN, 0);
845 if (ret)
846 goto reset_pin_count;
847
848 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
849 if (ret)
850 goto unpin_ctx_obj;
851
852 ctx_obj->dirty = true;
853 }
854
855 return ret;
856
857 unpin_ctx_obj:
858 i915_gem_object_ggtt_unpin(ctx_obj);
859 reset_pin_count:
860 ctx->engine[ring->id].pin_count = 0;
861
862 return ret;
863 }
864
intel_lr_context_unpin(struct intel_engine_cs * ring,struct intel_context * ctx)865 void intel_lr_context_unpin(struct intel_engine_cs *ring,
866 struct intel_context *ctx)
867 {
868 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
869 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
870
871 if (ctx_obj) {
872 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
873 if (--ctx->engine[ring->id].pin_count == 0) {
874 intel_unpin_ringbuffer_obj(ringbuf);
875 i915_gem_object_ggtt_unpin(ctx_obj);
876 }
877 }
878 }
879
logical_ring_alloc_request(struct intel_engine_cs * ring,struct intel_context * ctx)880 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
881 struct intel_context *ctx)
882 {
883 struct drm_i915_gem_request *request;
884 struct drm_i915_private *dev_private = ring->dev->dev_private;
885 int ret;
886
887 if (ring->outstanding_lazy_request)
888 return 0;
889
890 request = kzalloc(sizeof(*request), GFP_KERNEL);
891 if (request == NULL)
892 return -ENOMEM;
893
894 if (ctx != ring->default_context) {
895 ret = intel_lr_context_pin(ring, ctx);
896 if (ret) {
897 kfree(request);
898 return ret;
899 }
900 }
901
902 kref_init(&request->ref);
903 request->ring = ring;
904 request->uniq = dev_private->request_uniq++;
905
906 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
907 if (ret) {
908 intel_lr_context_unpin(ring, ctx);
909 kfree(request);
910 return ret;
911 }
912
913 request->ctx = ctx;
914 i915_gem_context_reference(request->ctx);
915 request->ringbuf = ctx->engine[ring->id].ringbuf;
916
917 ring->outstanding_lazy_request = request;
918 return 0;
919 }
920
logical_ring_wait_request(struct intel_ringbuffer * ringbuf,int bytes)921 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
922 int bytes)
923 {
924 struct intel_engine_cs *ring = ringbuf->ring;
925 struct drm_i915_gem_request *request;
926 int ret;
927
928 if (intel_ring_space(ringbuf) >= bytes)
929 return 0;
930
931 list_for_each_entry(request, &ring->request_list, list) {
932 /*
933 * The request queue is per-engine, so can contain requests
934 * from multiple ringbuffers. Here, we must ignore any that
935 * aren't from the ringbuffer we're considering.
936 */
937 struct intel_context *ctx = request->ctx;
938 if (ctx->engine[ring->id].ringbuf != ringbuf)
939 continue;
940
941 /* Would completion of this request free enough space? */
942 if (__intel_ring_space(request->tail, ringbuf->tail,
943 ringbuf->size) >= bytes) {
944 break;
945 }
946 }
947
948 if (&request->list == &ring->request_list)
949 return -ENOSPC;
950
951 ret = i915_wait_request(request);
952 if (ret)
953 return ret;
954
955 i915_gem_retire_requests_ring(ring);
956
957 return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
958 }
959
logical_ring_wait_for_space(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,int bytes)960 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
961 struct intel_context *ctx,
962 int bytes)
963 {
964 struct intel_engine_cs *ring = ringbuf->ring;
965 struct drm_device *dev = ring->dev;
966 struct drm_i915_private *dev_priv = dev->dev_private;
967 unsigned long end;
968 int ret;
969
970 ret = logical_ring_wait_request(ringbuf, bytes);
971 if (ret != -ENOSPC)
972 return ret;
973
974 /* Force the context submission in case we have been skipping it */
975 intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
976
977 /* With GEM the hangcheck timer should kick us out of the loop,
978 * leaving it early runs the risk of corrupting GEM state (due
979 * to running on almost untested codepaths). But on resume
980 * timers don't work yet, so prevent a complete hang in that
981 * case by choosing an insanely large timeout. */
982 end = jiffies + 60 * HZ;
983
984 ret = 0;
985 do {
986 if (intel_ring_space(ringbuf) >= bytes)
987 break;
988
989 msleep(1);
990
991 if (dev_priv->mm.interruptible && signal_pending(current)) {
992 ret = -ERESTARTSYS;
993 break;
994 }
995
996 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
997 dev_priv->mm.interruptible);
998 if (ret)
999 break;
1000
1001 if (time_after(jiffies, end)) {
1002 ret = -EBUSY;
1003 break;
1004 }
1005 } while (1);
1006
1007 return ret;
1008 }
1009
logical_ring_wrap_buffer(struct intel_ringbuffer * ringbuf,struct intel_context * ctx)1010 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
1011 struct intel_context *ctx)
1012 {
1013 uint32_t __iomem *virt;
1014 int rem = ringbuf->size - ringbuf->tail;
1015
1016 if (ringbuf->space < rem) {
1017 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
1018
1019 if (ret)
1020 return ret;
1021 }
1022
1023 virt = ringbuf->virtual_start + ringbuf->tail;
1024 rem /= 4;
1025 while (rem--)
1026 iowrite32(MI_NOOP, virt++);
1027
1028 ringbuf->tail = 0;
1029 intel_ring_update_space(ringbuf);
1030
1031 return 0;
1032 }
1033
logical_ring_prepare(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,int bytes)1034 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1035 struct intel_context *ctx, int bytes)
1036 {
1037 int ret;
1038
1039 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1040 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1041 if (unlikely(ret))
1042 return ret;
1043 }
1044
1045 if (unlikely(ringbuf->space < bytes)) {
1046 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1047 if (unlikely(ret))
1048 return ret;
1049 }
1050
1051 return 0;
1052 }
1053
1054 /**
1055 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1056 *
1057 * @ringbuf: Logical ringbuffer.
1058 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1059 *
1060 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1061 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1062 * and also preallocates a request (every workload submission is still mediated through
1063 * requests, same as it did with legacy ringbuffer submission).
1064 *
1065 * Return: non-zero if the ringbuffer is not ready to be written to.
1066 */
intel_logical_ring_begin(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,int num_dwords)1067 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1068 struct intel_context *ctx, int num_dwords)
1069 {
1070 struct intel_engine_cs *ring = ringbuf->ring;
1071 struct drm_device *dev = ring->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 int ret;
1074
1075 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1076 dev_priv->mm.interruptible);
1077 if (ret)
1078 return ret;
1079
1080 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1081 if (ret)
1082 return ret;
1083
1084 /* Preallocate the olr before touching the ring */
1085 ret = logical_ring_alloc_request(ring, ctx);
1086 if (ret)
1087 return ret;
1088
1089 ringbuf->space -= num_dwords * sizeof(uint32_t);
1090 return 0;
1091 }
1092
intel_logical_ring_workarounds_emit(struct intel_engine_cs * ring,struct intel_context * ctx)1093 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1094 struct intel_context *ctx)
1095 {
1096 int ret, i;
1097 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1098 struct drm_device *dev = ring->dev;
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 struct i915_workarounds *w = &dev_priv->workarounds;
1101
1102 if (WARN_ON_ONCE(w->count == 0))
1103 return 0;
1104
1105 ring->gpu_caches_dirty = true;
1106 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1107 if (ret)
1108 return ret;
1109
1110 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1111 if (ret)
1112 return ret;
1113
1114 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1115 for (i = 0; i < w->count; i++) {
1116 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1117 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1118 }
1119 intel_logical_ring_emit(ringbuf, MI_NOOP);
1120
1121 intel_logical_ring_advance(ringbuf);
1122
1123 ring->gpu_caches_dirty = true;
1124 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1125 if (ret)
1126 return ret;
1127
1128 return 0;
1129 }
1130
gen8_init_common_ring(struct intel_engine_cs * ring)1131 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1132 {
1133 struct drm_device *dev = ring->dev;
1134 struct drm_i915_private *dev_priv = dev->dev_private;
1135
1136 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1137 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1138
1139 if (ring->status_page.obj) {
1140 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1141 (u32)ring->status_page.gfx_addr);
1142 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1143 }
1144
1145 I915_WRITE(RING_MODE_GEN7(ring),
1146 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1147 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1148 POSTING_READ(RING_MODE_GEN7(ring));
1149 ring->next_context_status_buffer = 0;
1150 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1151
1152 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1153
1154 return 0;
1155 }
1156
gen8_init_render_ring(struct intel_engine_cs * ring)1157 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1158 {
1159 struct drm_device *dev = ring->dev;
1160 struct drm_i915_private *dev_priv = dev->dev_private;
1161 int ret;
1162
1163 ret = gen8_init_common_ring(ring);
1164 if (ret)
1165 return ret;
1166
1167 /* We need to disable the AsyncFlip performance optimisations in order
1168 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1169 * programmed to '1' on all products.
1170 *
1171 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1172 */
1173 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1174
1175 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1176
1177 return init_workarounds_ring(ring);
1178 }
1179
gen9_init_render_ring(struct intel_engine_cs * ring)1180 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1181 {
1182 int ret;
1183
1184 ret = gen8_init_common_ring(ring);
1185 if (ret)
1186 return ret;
1187
1188 return init_workarounds_ring(ring);
1189 }
1190
gen8_emit_bb_start(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,u64 offset,unsigned dispatch_flags)1191 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1192 struct intel_context *ctx,
1193 u64 offset, unsigned dispatch_flags)
1194 {
1195 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1196 int ret;
1197
1198 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1199 if (ret)
1200 return ret;
1201
1202 /* FIXME(BDW): Address space and security selectors. */
1203 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1204 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1205 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1206 intel_logical_ring_emit(ringbuf, MI_NOOP);
1207 intel_logical_ring_advance(ringbuf);
1208
1209 return 0;
1210 }
1211
gen8_logical_ring_get_irq(struct intel_engine_cs * ring)1212 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1213 {
1214 struct drm_device *dev = ring->dev;
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216 unsigned long flags;
1217
1218 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1219 return false;
1220
1221 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1222 if (ring->irq_refcount++ == 0) {
1223 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1224 POSTING_READ(RING_IMR(ring->mmio_base));
1225 }
1226 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1227
1228 return true;
1229 }
1230
gen8_logical_ring_put_irq(struct intel_engine_cs * ring)1231 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1232 {
1233 struct drm_device *dev = ring->dev;
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 unsigned long flags;
1236
1237 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1238 if (--ring->irq_refcount == 0) {
1239 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1240 POSTING_READ(RING_IMR(ring->mmio_base));
1241 }
1242 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1243 }
1244
gen8_emit_flush(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,u32 invalidate_domains,u32 unused)1245 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1246 struct intel_context *ctx,
1247 u32 invalidate_domains,
1248 u32 unused)
1249 {
1250 struct intel_engine_cs *ring = ringbuf->ring;
1251 struct drm_device *dev = ring->dev;
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253 uint32_t cmd;
1254 int ret;
1255
1256 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1257 if (ret)
1258 return ret;
1259
1260 cmd = MI_FLUSH_DW + 1;
1261
1262 /* We always require a command barrier so that subsequent
1263 * commands, such as breadcrumb interrupts, are strictly ordered
1264 * wrt the contents of the write cache being flushed to memory
1265 * (and thus being coherent from the CPU).
1266 */
1267 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1268
1269 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1270 cmd |= MI_INVALIDATE_TLB;
1271 if (ring == &dev_priv->ring[VCS])
1272 cmd |= MI_INVALIDATE_BSD;
1273 }
1274
1275 intel_logical_ring_emit(ringbuf, cmd);
1276 intel_logical_ring_emit(ringbuf,
1277 I915_GEM_HWS_SCRATCH_ADDR |
1278 MI_FLUSH_DW_USE_GTT);
1279 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1280 intel_logical_ring_emit(ringbuf, 0); /* value */
1281 intel_logical_ring_advance(ringbuf);
1282
1283 return 0;
1284 }
1285
gen8_emit_flush_render(struct intel_ringbuffer * ringbuf,struct intel_context * ctx,u32 invalidate_domains,u32 flush_domains)1286 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1287 struct intel_context *ctx,
1288 u32 invalidate_domains,
1289 u32 flush_domains)
1290 {
1291 struct intel_engine_cs *ring = ringbuf->ring;
1292 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1293 u32 flags = 0;
1294 int ret;
1295
1296 flags |= PIPE_CONTROL_CS_STALL;
1297
1298 if (flush_domains) {
1299 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1300 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1301 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1302 }
1303
1304 if (invalidate_domains) {
1305 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1306 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1307 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1308 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1309 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1310 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1311 flags |= PIPE_CONTROL_QW_WRITE;
1312 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1313 }
1314
1315 ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1316 if (ret)
1317 return ret;
1318
1319 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1320 intel_logical_ring_emit(ringbuf, flags);
1321 intel_logical_ring_emit(ringbuf, scratch_addr);
1322 intel_logical_ring_emit(ringbuf, 0);
1323 intel_logical_ring_emit(ringbuf, 0);
1324 intel_logical_ring_emit(ringbuf, 0);
1325 intel_logical_ring_advance(ringbuf);
1326
1327 return 0;
1328 }
1329
gen8_get_seqno(struct intel_engine_cs * ring,bool lazy_coherency)1330 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1331 {
1332 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1333 }
1334
gen8_set_seqno(struct intel_engine_cs * ring,u32 seqno)1335 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1336 {
1337 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1338 }
1339
gen8_emit_request(struct intel_ringbuffer * ringbuf,struct drm_i915_gem_request * request)1340 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1341 struct drm_i915_gem_request *request)
1342 {
1343 struct intel_engine_cs *ring = ringbuf->ring;
1344 u32 cmd;
1345 int ret;
1346
1347 /*
1348 * Reserve space for 2 NOOPs at the end of each request to be
1349 * used as a workaround for not being allowed to do lite
1350 * restore with HEAD==TAIL (WaIdleLiteRestore).
1351 */
1352 ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
1353 if (ret)
1354 return ret;
1355
1356 cmd = MI_STORE_DWORD_IMM_GEN4;
1357 cmd |= MI_GLOBAL_GTT;
1358
1359 intel_logical_ring_emit(ringbuf, cmd);
1360 intel_logical_ring_emit(ringbuf,
1361 (ring->status_page.gfx_addr +
1362 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1363 intel_logical_ring_emit(ringbuf, 0);
1364 intel_logical_ring_emit(ringbuf,
1365 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1366 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1367 intel_logical_ring_emit(ringbuf, MI_NOOP);
1368 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1369
1370 /*
1371 * Here we add two extra NOOPs as padding to avoid
1372 * lite restore of a context with HEAD==TAIL.
1373 */
1374 intel_logical_ring_emit(ringbuf, MI_NOOP);
1375 intel_logical_ring_emit(ringbuf, MI_NOOP);
1376 intel_logical_ring_advance(ringbuf);
1377
1378 return 0;
1379 }
1380
intel_lr_context_render_state_init(struct intel_engine_cs * ring,struct intel_context * ctx)1381 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1382 struct intel_context *ctx)
1383 {
1384 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1385 struct render_state so;
1386 struct drm_i915_file_private *file_priv = ctx->file_priv;
1387 struct drm_file *file = file_priv ? file_priv->file : NULL;
1388 int ret;
1389
1390 ret = i915_gem_render_state_prepare(ring, &so);
1391 if (ret)
1392 return ret;
1393
1394 if (so.rodata == NULL)
1395 return 0;
1396
1397 ret = ring->emit_bb_start(ringbuf,
1398 ctx,
1399 so.ggtt_offset,
1400 I915_DISPATCH_SECURE);
1401 if (ret)
1402 goto out;
1403
1404 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1405
1406 ret = __i915_add_request(ring, file, so.obj);
1407 /* intel_logical_ring_add_request moves object to inactive if it
1408 * fails */
1409 out:
1410 i915_gem_render_state_fini(&so);
1411 return ret;
1412 }
1413
gen8_init_rcs_context(struct intel_engine_cs * ring,struct intel_context * ctx)1414 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1415 struct intel_context *ctx)
1416 {
1417 int ret;
1418
1419 ret = intel_logical_ring_workarounds_emit(ring, ctx);
1420 if (ret)
1421 return ret;
1422
1423 return intel_lr_context_render_state_init(ring, ctx);
1424 }
1425
1426 /**
1427 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1428 *
1429 * @ring: Engine Command Streamer.
1430 *
1431 */
intel_logical_ring_cleanup(struct intel_engine_cs * ring)1432 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1433 {
1434 struct drm_i915_private *dev_priv;
1435
1436 if (!intel_ring_initialized(ring))
1437 return;
1438
1439 dev_priv = ring->dev->dev_private;
1440
1441 intel_logical_ring_stop(ring);
1442 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1443 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1444
1445 if (ring->cleanup)
1446 ring->cleanup(ring);
1447
1448 i915_cmd_parser_fini_ring(ring);
1449
1450 if (ring->status_page.obj) {
1451 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1452 ring->status_page.obj = NULL;
1453 }
1454 }
1455
logical_ring_init(struct drm_device * dev,struct intel_engine_cs * ring)1456 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1457 {
1458 int ret;
1459
1460 /* Intentionally left blank. */
1461 ring->buffer = NULL;
1462
1463 ring->dev = dev;
1464 INIT_LIST_HEAD(&ring->active_list);
1465 INIT_LIST_HEAD(&ring->request_list);
1466 init_waitqueue_head(&ring->irq_queue);
1467
1468 INIT_LIST_HEAD(&ring->execlist_queue);
1469 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1470 spin_lock_init(&ring->execlist_lock);
1471
1472 ret = i915_cmd_parser_init_ring(ring);
1473 if (ret)
1474 return ret;
1475
1476 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1477
1478 return ret;
1479 }
1480
logical_render_ring_init(struct drm_device * dev)1481 static int logical_render_ring_init(struct drm_device *dev)
1482 {
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1485 int ret;
1486
1487 ring->name = "render ring";
1488 ring->id = RCS;
1489 ring->mmio_base = RENDER_RING_BASE;
1490 ring->irq_enable_mask =
1491 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1492 ring->irq_keep_mask =
1493 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1494 if (HAS_L3_DPF(dev))
1495 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1496
1497 if (INTEL_INFO(dev)->gen >= 9)
1498 ring->init_hw = gen9_init_render_ring;
1499 else
1500 ring->init_hw = gen8_init_render_ring;
1501 ring->init_context = gen8_init_rcs_context;
1502 ring->cleanup = intel_fini_pipe_control;
1503 ring->get_seqno = gen8_get_seqno;
1504 ring->set_seqno = gen8_set_seqno;
1505 ring->emit_request = gen8_emit_request;
1506 ring->emit_flush = gen8_emit_flush_render;
1507 ring->irq_get = gen8_logical_ring_get_irq;
1508 ring->irq_put = gen8_logical_ring_put_irq;
1509 ring->emit_bb_start = gen8_emit_bb_start;
1510
1511 ring->dev = dev;
1512 ret = logical_ring_init(dev, ring);
1513 if (ret)
1514 return ret;
1515
1516 return intel_init_pipe_control(ring);
1517 }
1518
logical_bsd_ring_init(struct drm_device * dev)1519 static int logical_bsd_ring_init(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1523
1524 ring->name = "bsd ring";
1525 ring->id = VCS;
1526 ring->mmio_base = GEN6_BSD_RING_BASE;
1527 ring->irq_enable_mask =
1528 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1529 ring->irq_keep_mask =
1530 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1531
1532 ring->init_hw = gen8_init_common_ring;
1533 ring->get_seqno = gen8_get_seqno;
1534 ring->set_seqno = gen8_set_seqno;
1535 ring->emit_request = gen8_emit_request;
1536 ring->emit_flush = gen8_emit_flush;
1537 ring->irq_get = gen8_logical_ring_get_irq;
1538 ring->irq_put = gen8_logical_ring_put_irq;
1539 ring->emit_bb_start = gen8_emit_bb_start;
1540
1541 return logical_ring_init(dev, ring);
1542 }
1543
logical_bsd2_ring_init(struct drm_device * dev)1544 static int logical_bsd2_ring_init(struct drm_device *dev)
1545 {
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1548
1549 ring->name = "bds2 ring";
1550 ring->id = VCS2;
1551 ring->mmio_base = GEN8_BSD2_RING_BASE;
1552 ring->irq_enable_mask =
1553 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1554 ring->irq_keep_mask =
1555 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1556
1557 ring->init_hw = gen8_init_common_ring;
1558 ring->get_seqno = gen8_get_seqno;
1559 ring->set_seqno = gen8_set_seqno;
1560 ring->emit_request = gen8_emit_request;
1561 ring->emit_flush = gen8_emit_flush;
1562 ring->irq_get = gen8_logical_ring_get_irq;
1563 ring->irq_put = gen8_logical_ring_put_irq;
1564 ring->emit_bb_start = gen8_emit_bb_start;
1565
1566 return logical_ring_init(dev, ring);
1567 }
1568
logical_blt_ring_init(struct drm_device * dev)1569 static int logical_blt_ring_init(struct drm_device *dev)
1570 {
1571 struct drm_i915_private *dev_priv = dev->dev_private;
1572 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1573
1574 ring->name = "blitter ring";
1575 ring->id = BCS;
1576 ring->mmio_base = BLT_RING_BASE;
1577 ring->irq_enable_mask =
1578 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1579 ring->irq_keep_mask =
1580 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1581
1582 ring->init_hw = gen8_init_common_ring;
1583 ring->get_seqno = gen8_get_seqno;
1584 ring->set_seqno = gen8_set_seqno;
1585 ring->emit_request = gen8_emit_request;
1586 ring->emit_flush = gen8_emit_flush;
1587 ring->irq_get = gen8_logical_ring_get_irq;
1588 ring->irq_put = gen8_logical_ring_put_irq;
1589 ring->emit_bb_start = gen8_emit_bb_start;
1590
1591 return logical_ring_init(dev, ring);
1592 }
1593
logical_vebox_ring_init(struct drm_device * dev)1594 static int logical_vebox_ring_init(struct drm_device *dev)
1595 {
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1598
1599 ring->name = "video enhancement ring";
1600 ring->id = VECS;
1601 ring->mmio_base = VEBOX_RING_BASE;
1602 ring->irq_enable_mask =
1603 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1604 ring->irq_keep_mask =
1605 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1606
1607 ring->init_hw = gen8_init_common_ring;
1608 ring->get_seqno = gen8_get_seqno;
1609 ring->set_seqno = gen8_set_seqno;
1610 ring->emit_request = gen8_emit_request;
1611 ring->emit_flush = gen8_emit_flush;
1612 ring->irq_get = gen8_logical_ring_get_irq;
1613 ring->irq_put = gen8_logical_ring_put_irq;
1614 ring->emit_bb_start = gen8_emit_bb_start;
1615
1616 return logical_ring_init(dev, ring);
1617 }
1618
1619 /**
1620 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1621 * @dev: DRM device.
1622 *
1623 * This function inits the engines for an Execlists submission style (the equivalent in the
1624 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1625 * those engines that are present in the hardware.
1626 *
1627 * Return: non-zero if the initialization failed.
1628 */
intel_logical_rings_init(struct drm_device * dev)1629 int intel_logical_rings_init(struct drm_device *dev)
1630 {
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 int ret;
1633
1634 ret = logical_render_ring_init(dev);
1635 if (ret)
1636 return ret;
1637
1638 if (HAS_BSD(dev)) {
1639 ret = logical_bsd_ring_init(dev);
1640 if (ret)
1641 goto cleanup_render_ring;
1642 }
1643
1644 if (HAS_BLT(dev)) {
1645 ret = logical_blt_ring_init(dev);
1646 if (ret)
1647 goto cleanup_bsd_ring;
1648 }
1649
1650 if (HAS_VEBOX(dev)) {
1651 ret = logical_vebox_ring_init(dev);
1652 if (ret)
1653 goto cleanup_blt_ring;
1654 }
1655
1656 if (HAS_BSD2(dev)) {
1657 ret = logical_bsd2_ring_init(dev);
1658 if (ret)
1659 goto cleanup_vebox_ring;
1660 }
1661
1662 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1663 if (ret)
1664 goto cleanup_bsd2_ring;
1665
1666 return 0;
1667
1668 cleanup_bsd2_ring:
1669 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1670 cleanup_vebox_ring:
1671 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1672 cleanup_blt_ring:
1673 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1674 cleanup_bsd_ring:
1675 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1676 cleanup_render_ring:
1677 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1678
1679 return ret;
1680 }
1681
1682 static u32
make_rpcs(struct drm_device * dev)1683 make_rpcs(struct drm_device *dev)
1684 {
1685 u32 rpcs = 0;
1686
1687 /*
1688 * No explicit RPCS request is needed to ensure full
1689 * slice/subslice/EU enablement prior to Gen9.
1690 */
1691 if (INTEL_INFO(dev)->gen < 9)
1692 return 0;
1693
1694 /*
1695 * Starting in Gen9, render power gating can leave
1696 * slice/subslice/EU in a partially enabled state. We
1697 * must make an explicit request through RPCS for full
1698 * enablement.
1699 */
1700 if (INTEL_INFO(dev)->has_slice_pg) {
1701 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1702 rpcs |= INTEL_INFO(dev)->slice_total <<
1703 GEN8_RPCS_S_CNT_SHIFT;
1704 rpcs |= GEN8_RPCS_ENABLE;
1705 }
1706
1707 if (INTEL_INFO(dev)->has_subslice_pg) {
1708 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1709 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
1710 GEN8_RPCS_SS_CNT_SHIFT;
1711 rpcs |= GEN8_RPCS_ENABLE;
1712 }
1713
1714 if (INTEL_INFO(dev)->has_eu_pg) {
1715 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1716 GEN8_RPCS_EU_MIN_SHIFT;
1717 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1718 GEN8_RPCS_EU_MAX_SHIFT;
1719 rpcs |= GEN8_RPCS_ENABLE;
1720 }
1721
1722 return rpcs;
1723 }
1724
1725 static int
populate_lr_context(struct intel_context * ctx,struct drm_i915_gem_object * ctx_obj,struct intel_engine_cs * ring,struct intel_ringbuffer * ringbuf)1726 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1727 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1728 {
1729 struct drm_device *dev = ring->dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1732 struct page *page;
1733 uint32_t *reg_state;
1734 int ret;
1735
1736 if (!ppgtt)
1737 ppgtt = dev_priv->mm.aliasing_ppgtt;
1738
1739 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1740 if (ret) {
1741 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1742 return ret;
1743 }
1744
1745 ret = i915_gem_object_get_pages(ctx_obj);
1746 if (ret) {
1747 DRM_DEBUG_DRIVER("Could not get object pages\n");
1748 return ret;
1749 }
1750
1751 i915_gem_object_pin_pages(ctx_obj);
1752
1753 /* The second page of the context object contains some fields which must
1754 * be set up prior to the first execution. */
1755 page = i915_gem_object_get_page(ctx_obj, 1);
1756 reg_state = kmap_atomic(page);
1757
1758 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1759 * commands followed by (reg, value) pairs. The values we are setting here are
1760 * only for the first context restore: on a subsequent save, the GPU will
1761 * recreate this batchbuffer with new values (including all the missing
1762 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1763 if (ring->id == RCS)
1764 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1765 else
1766 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1767 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1768 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1769 reg_state[CTX_CONTEXT_CONTROL+1] =
1770 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1771 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
1772 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1773 reg_state[CTX_RING_HEAD+1] = 0;
1774 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1775 reg_state[CTX_RING_TAIL+1] = 0;
1776 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1777 /* Ring buffer start address is not known until the buffer is pinned.
1778 * It is written to the context image in execlists_update_context()
1779 */
1780 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1781 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1782 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1783 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1784 reg_state[CTX_BB_HEAD_U+1] = 0;
1785 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1786 reg_state[CTX_BB_HEAD_L+1] = 0;
1787 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1788 reg_state[CTX_BB_STATE+1] = (1<<5);
1789 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1790 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1791 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1792 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1793 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1794 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1795 if (ring->id == RCS) {
1796 /* TODO: according to BSpec, the register state context
1797 * for CHV does not have these. OTOH, these registers do
1798 * exist in CHV. I'm waiting for a clarification */
1799 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1800 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1801 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1802 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1803 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1804 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1805 }
1806 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1807 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1808 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1809 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1810 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1811 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1812 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1813 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1814 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1815 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1816 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1817 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1818 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr);
1819 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr);
1820 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr);
1821 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr);
1822 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr);
1823 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr);
1824 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr);
1825 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr);
1826 if (ring->id == RCS) {
1827 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1828 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
1829 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
1830 }
1831
1832 kunmap_atomic(reg_state);
1833
1834 ctx_obj->dirty = 1;
1835 set_page_dirty(page);
1836 i915_gem_object_unpin_pages(ctx_obj);
1837
1838 return 0;
1839 }
1840
1841 /**
1842 * intel_lr_context_free() - free the LRC specific bits of a context
1843 * @ctx: the LR context to free.
1844 *
1845 * The real context freeing is done in i915_gem_context_free: this only
1846 * takes care of the bits that are LRC related: the per-engine backing
1847 * objects and the logical ringbuffer.
1848 */
intel_lr_context_free(struct intel_context * ctx)1849 void intel_lr_context_free(struct intel_context *ctx)
1850 {
1851 int i;
1852
1853 for (i = 0; i < I915_NUM_RINGS; i++) {
1854 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1855
1856 if (ctx_obj) {
1857 struct intel_ringbuffer *ringbuf =
1858 ctx->engine[i].ringbuf;
1859 struct intel_engine_cs *ring = ringbuf->ring;
1860
1861 if (ctx == ring->default_context) {
1862 intel_unpin_ringbuffer_obj(ringbuf);
1863 i915_gem_object_ggtt_unpin(ctx_obj);
1864 }
1865 WARN_ON(ctx->engine[ring->id].pin_count);
1866 intel_destroy_ringbuffer_obj(ringbuf);
1867 kfree(ringbuf);
1868 drm_gem_object_unreference(&ctx_obj->base);
1869 }
1870 }
1871 }
1872
get_lr_context_size(struct intel_engine_cs * ring)1873 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1874 {
1875 int ret = 0;
1876
1877 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1878
1879 switch (ring->id) {
1880 case RCS:
1881 if (INTEL_INFO(ring->dev)->gen >= 9)
1882 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1883 else
1884 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1885 break;
1886 case VCS:
1887 case BCS:
1888 case VECS:
1889 case VCS2:
1890 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1891 break;
1892 }
1893
1894 return ret;
1895 }
1896
lrc_setup_hardware_status_page(struct intel_engine_cs * ring,struct drm_i915_gem_object * default_ctx_obj)1897 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1898 struct drm_i915_gem_object *default_ctx_obj)
1899 {
1900 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1901
1902 /* The status page is offset 0 from the default context object
1903 * in LRC mode. */
1904 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1905 ring->status_page.page_addr =
1906 kmap(sg_page(default_ctx_obj->pages->sgl));
1907 ring->status_page.obj = default_ctx_obj;
1908
1909 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1910 (u32)ring->status_page.gfx_addr);
1911 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1912 }
1913
1914 /**
1915 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1916 * @ctx: LR context to create.
1917 * @ring: engine to be used with the context.
1918 *
1919 * This function can be called more than once, with different engines, if we plan
1920 * to use the context with them. The context backing objects and the ringbuffers
1921 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1922 * the creation is a deferred call: it's better to make sure first that we need to use
1923 * a given ring with the context.
1924 *
1925 * Return: non-zero on error.
1926 */
intel_lr_context_deferred_create(struct intel_context * ctx,struct intel_engine_cs * ring)1927 int intel_lr_context_deferred_create(struct intel_context *ctx,
1928 struct intel_engine_cs *ring)
1929 {
1930 const bool is_global_default_ctx = (ctx == ring->default_context);
1931 struct drm_device *dev = ring->dev;
1932 struct drm_i915_gem_object *ctx_obj;
1933 uint32_t context_size;
1934 struct intel_ringbuffer *ringbuf;
1935 int ret;
1936
1937 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1938 WARN_ON(ctx->engine[ring->id].state);
1939
1940 context_size = round_up(get_lr_context_size(ring), 4096);
1941
1942 ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1943 if (IS_ERR(ctx_obj)) {
1944 ret = PTR_ERR(ctx_obj);
1945 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1946 return ret;
1947 }
1948
1949 if (is_global_default_ctx) {
1950 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1951 if (ret) {
1952 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1953 ret);
1954 drm_gem_object_unreference(&ctx_obj->base);
1955 return ret;
1956 }
1957 }
1958
1959 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1960 if (!ringbuf) {
1961 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1962 ring->name);
1963 ret = -ENOMEM;
1964 goto error_unpin_ctx;
1965 }
1966
1967 ringbuf->ring = ring;
1968
1969 ringbuf->size = 32 * PAGE_SIZE;
1970 ringbuf->effective_size = ringbuf->size;
1971 ringbuf->head = 0;
1972 ringbuf->tail = 0;
1973 ringbuf->last_retired_head = -1;
1974 intel_ring_update_space(ringbuf);
1975
1976 if (ringbuf->obj == NULL) {
1977 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1978 if (ret) {
1979 DRM_DEBUG_DRIVER(
1980 "Failed to allocate ringbuffer obj %s: %d\n",
1981 ring->name, ret);
1982 goto error_free_rbuf;
1983 }
1984
1985 if (is_global_default_ctx) {
1986 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1987 if (ret) {
1988 DRM_ERROR(
1989 "Failed to pin and map ringbuffer %s: %d\n",
1990 ring->name, ret);
1991 goto error_destroy_rbuf;
1992 }
1993 }
1994
1995 }
1996
1997 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1998 if (ret) {
1999 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2000 goto error;
2001 }
2002
2003 ctx->engine[ring->id].ringbuf = ringbuf;
2004 ctx->engine[ring->id].state = ctx_obj;
2005
2006 if (ctx == ring->default_context)
2007 lrc_setup_hardware_status_page(ring, ctx_obj);
2008 else if (ring->id == RCS && !ctx->rcs_initialized) {
2009 if (ring->init_context) {
2010 ret = ring->init_context(ring, ctx);
2011 if (ret) {
2012 DRM_ERROR("ring init context: %d\n", ret);
2013 ctx->engine[ring->id].ringbuf = NULL;
2014 ctx->engine[ring->id].state = NULL;
2015 goto error;
2016 }
2017 }
2018
2019 ctx->rcs_initialized = true;
2020 }
2021
2022 return 0;
2023
2024 error:
2025 if (is_global_default_ctx)
2026 intel_unpin_ringbuffer_obj(ringbuf);
2027 error_destroy_rbuf:
2028 intel_destroy_ringbuffer_obj(ringbuf);
2029 error_free_rbuf:
2030 kfree(ringbuf);
2031 error_unpin_ctx:
2032 if (is_global_default_ctx)
2033 i915_gem_object_ggtt_unpin(ctx_obj);
2034 drm_gem_object_unreference(&ctx_obj->base);
2035 return ret;
2036 }
2037
intel_lr_context_reset(struct drm_device * dev,struct intel_context * ctx)2038 void intel_lr_context_reset(struct drm_device *dev,
2039 struct intel_context *ctx)
2040 {
2041 struct drm_i915_private *dev_priv = dev->dev_private;
2042 struct intel_engine_cs *ring;
2043 int i;
2044
2045 for_each_ring(ring, dev_priv, i) {
2046 struct drm_i915_gem_object *ctx_obj =
2047 ctx->engine[ring->id].state;
2048 struct intel_ringbuffer *ringbuf =
2049 ctx->engine[ring->id].ringbuf;
2050 uint32_t *reg_state;
2051 struct page *page;
2052
2053 if (!ctx_obj)
2054 continue;
2055
2056 if (i915_gem_object_get_pages(ctx_obj)) {
2057 WARN(1, "Failed get_pages for context obj\n");
2058 continue;
2059 }
2060 page = i915_gem_object_get_page(ctx_obj, 1);
2061 reg_state = kmap_atomic(page);
2062
2063 reg_state[CTX_RING_HEAD+1] = 0;
2064 reg_state[CTX_RING_TAIL+1] = 0;
2065
2066 kunmap_atomic(reg_state);
2067
2068 ringbuf->head = 0;
2069 ringbuf->tail = 0;
2070 }
2071 }
2072