Searched defs:i0 (Results 1 - 14 of 14) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/msm/dsi/
H A Dmmss_cc.xml.h63 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } REG_MMSS_CC_CLK() argument
65 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } REG_MMSS_CC_CLK_CC() argument
82 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } REG_MMSS_CC_CLK_MD() argument
96 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } REG_MMSS_CC_CLK_NS() argument
H A Ddsi.xml.h347 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } REG_DSI_RDBK() argument
349 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } REG_DSI_RDBK_DATA() argument
550 static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; } REG_DSI_8960_LN() argument
552 static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; } REG_DSI_8960_LN_CFG_0() argument
554 static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; } REG_DSI_8960_LN_CFG_1() argument
556 static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; } REG_DSI_8960_LN_CFG_2() argument
558 static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; } REG_DSI_8960_LN_TEST_DATAPATH() argument
560 static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; } REG_DSI_8960_LN_TEST_STR_0() argument
562 static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; } REG_DSI_8960_LN_TEST_STR_1() argument
659 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } REG_DSI_28nm_PHY_LN() argument
661 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } REG_DSI_28nm_PHY_LN_CFG_0() argument
663 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } REG_DSI_28nm_PHY_LN_CFG_1() argument
665 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } REG_DSI_28nm_PHY_LN_CFG_2() argument
667 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } REG_DSI_28nm_PHY_LN_CFG_3() argument
669 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } REG_DSI_28nm_PHY_LN_CFG_4() argument
671 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } REG_DSI_28nm_PHY_LN_TEST_DATAPATH() argument
673 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } REG_DSI_28nm_PHY_LN_DEBUG_SEL() argument
675 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } REG_DSI_28nm_PHY_LN_TEST_STR_0() argument
677 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } REG_DSI_28nm_PHY_LN_TEST_STR_1() argument
/linux-4.1.27/arch/blackfin/include/asm/
H A Dcontext.S269 i0 = [sp++]; define
339 i0 = [sp++]; define
/linux-4.1.27/fs/jffs2/
H A Dcompr_rubin.c105 long i0, i1; encode() local
203 long i0, threshold; decode() local
/linux-4.1.27/arch/blackfin/include/uapi/asm/
H A Dptrace.h68 long i0; member in struct:pt_regs
/linux-4.1.27/sound/pci/cs46xx/
H A Dcs46xx_dsp_scb_types.h1125 u32 i0; member in struct:dsp_magic_snoop_task
/linux-4.1.27/drivers/gpu/drm/msm/edp/
H A Dedp.xml.h275 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } REG_EDP_PHY_LN() argument
277 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } argument
/linux-4.1.27/fs/jfs/
H A Djfs_dmap.c3388 int i, i0 = true, j, j0 = true, k, n; dbExtendFS() local
/linux-4.1.27/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h144 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } REG_HDMI_AVI_INFO() argument
148 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } REG_HDMI_GENERIC0() argument
152 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } REG_HDMI_GENERIC1() argument
154 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } REG_HDMI_ACR() argument
156 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } REG_HDMI_ACR_0() argument
164 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } REG_HDMI_ACR_1() argument
361 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } REG_HDMI_I2C_TRANSACTION() argument
363 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } REG_HDMI_I2C_TRANSACTION_REG() argument
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4.xml.h318 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } REG_MDP4_OVLP() argument
320 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } REG_MDP4_OVLP_CFG() argument
322 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } REG_MDP4_OVLP_SIZE() argument
336 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } REG_MDP4_OVLP_BASE() argument
338 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } REG_MDP4_OVLP_STRIDE() argument
340 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } REG_MDP4_OVLP_OPMODE() argument
352 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE() argument
354 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_OP() argument
374 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
376 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
378 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
380 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
382 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
384 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
396 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } REG_MDP4_OVLP_STAGE_CO3() argument
398 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } REG_MDP4_OVLP_STAGE_CO3_SEL() argument
401 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); } REG_MDP4_OVLP_TRANSP_LOW0() argument
403 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); } REG_MDP4_OVLP_TRANSP_LOW1() argument
405 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); } REG_MDP4_OVLP_TRANSP_HIGH0() argument
407 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); } REG_MDP4_OVLP_TRANSP_HIGH1() argument
409 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); } REG_MDP4_OVLP_CSC_CONFIG() argument
411 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } REG_MDP4_OVLP_CSC() argument
414 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_MV() argument
416 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_MV_VAL() argument
418 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_BV() argument
420 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument
422 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_BV() argument
424 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_BV_VAL() argument
426 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_LV() argument
428 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument
430 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_LV() argument
432 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_LV_VAL() argument
436 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } REG_MDP4_LUTN() argument
438 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } REG_MDP4_LUTN_LUT() argument
440 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } REG_MDP4_LUTN_LUT_VAL() argument
444 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } REG_MDP4_DMA_E_QUANT() argument
455 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } REG_MDP4_DMA() argument
457 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } REG_MDP4_DMA_CONFIG() argument
486 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } REG_MDP4_DMA_SRC_SIZE() argument
500 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } REG_MDP4_DMA_SRC_BASE() argument
502 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } REG_MDP4_DMA_SRC_STRIDE() argument
504 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } REG_MDP4_DMA_DST_SIZE() argument
518 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } REG_MDP4_DMA_CURSOR_SIZE() argument
532 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); } REG_MDP4_DMA_CURSOR_BASE() argument
534 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); } REG_MDP4_DMA_CURSOR_POS() argument
548 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); } REG_MDP4_DMA_CURSOR_BLEND_CONFIG() argument
558 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); } REG_MDP4_DMA_CURSOR_BLEND_PARAM() argument
560 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); } REG_MDP4_DMA_BLEND_TRANS_LOW() argument
562 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); } REG_MDP4_DMA_BLEND_TRANS_HIGH() argument
564 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); } REG_MDP4_DMA_FETCH_CONFIG() argument
566 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } REG_MDP4_DMA_CSC() argument
569 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_MV() argument
571 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_MV_VAL() argument
573 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_BV() argument
575 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_BV_VAL() argument
577 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_BV() argument
579 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_BV_VAL() argument
581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_LV() argument
583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_LV_VAL() argument
585 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_LV() argument
587 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_LV_VAL() argument
589 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } REG_MDP4_PIPE() argument
591 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } REG_MDP4_PIPE_SRC_SIZE() argument
605 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } REG_MDP4_PIPE_SRC_XY() argument
619 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } REG_MDP4_PIPE_DST_SIZE() argument
633 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } REG_MDP4_PIPE_DST_XY() argument
647 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } REG_MDP4_PIPE_SRCP0_BASE() argument
649 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } REG_MDP4_PIPE_SRCP1_BASE() argument
651 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } REG_MDP4_PIPE_SRCP2_BASE() argument
653 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; } REG_MDP4_PIPE_SRCP3_BASE() argument
655 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } REG_MDP4_PIPE_SRC_STRIDE_A() argument
669 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } REG_MDP4_PIPE_SRC_STRIDE_B() argument
683 static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } REG_MDP4_PIPE_FRAME_SIZE() argument
697 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } REG_MDP4_PIPE_SRC_FORMAT() argument
758 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } REG_MDP4_PIPE_SRC_UNPACK() argument
784 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } REG_MDP4_PIPE_OP_MODE() argument
809 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } REG_MDP4_PIPE_PHASEX_STEP() argument
811 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } REG_MDP4_PIPE_PHASEY_STEP() argument
813 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } REG_MDP4_PIPE_FETCH_CONFIG() argument
815 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } REG_MDP4_PIPE_SOLID_COLOR() argument
817 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } REG_MDP4_PIPE_CSC() argument
820 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_MV() argument
822 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_MV_VAL() argument
824 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_BV() argument
826 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument
828 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_BV() argument
830 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_BV_VAL() argument
832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_LV() argument
834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument
836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_LV() argument
838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_LV_VAL() argument
937 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } REG_MDP4_LCDC_LVDS_MUX_CTL() argument
939 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; } REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0() argument
965 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; } REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4() argument
/linux-4.1.27/drivers/gpu/drm/msm/adreno/
H A Da2xx.xml.h454 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } REG_A2XX_VSC_PIPE() argument
456 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } REG_A2XX_VSC_PIPE_CONFIG() argument
458 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } REG_A2XX_VSC_PIPE_DATA_ADDRESS() argument
460 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } REG_A2XX_VSC_PIPE_DATA_LENGTH() argument
H A Da4xx.xml.h291 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } REG_A4XX_RB_MRT() argument
293 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } REG_A4XX_RB_MRT_CONTROL() argument
306 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } REG_A4XX_RB_MRT_BUF_INFO() argument
332 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } REG_A4XX_RB_MRT_BASE() argument
334 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } REG_A4XX_RB_MRT_CONTROL3() argument
342 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } REG_A4XX_RB_MRT_BLEND_CONTROL() argument
710 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } REG_A4XX_RB_VPORT_Z_CLAMP() argument
712 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } REG_A4XX_RB_VPORT_Z_CLAMP_MIN() argument
714 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } REG_A4XX_RB_VPORT_Z_CLAMP_MAX() argument
720 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_TP() argument
722 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_TP_REG() argument
724 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL2_TP() argument
726 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL2_TP_REG() argument
728 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } REG_A4XX_RBBM_CLOCK_HYST_TP() argument
730 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } REG_A4XX_RBBM_CLOCK_HYST_TP_REG() argument
732 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_DELAY_TP() argument
734 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_DELAY_TP_REG() argument
810 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_SP() argument
812 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_SP_REG() argument
814 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL2_SP() argument
816 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL2_SP_REG() argument
818 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_HYST_SP() argument
820 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_HYST_SP_REG() argument
822 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_DELAY_SP() argument
824 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_DELAY_SP_REG() argument
826 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_RB() argument
828 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_RB_REG() argument
830 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL2_RB() argument
832 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL2_RB_REG() argument
834 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU() argument
836 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG() argument
838 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU() argument
840 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG() argument
854 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1() argument
856 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG() argument
977 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } REG_A4XX_CP_PROTECT() argument
979 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } REG_A4XX_CP_PROTECT_REG() argument
1001 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } REG_A4XX_CP_SCRATCH() argument
1003 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } REG_A4XX_CP_SCRATCH_REG() argument
1084 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } REG_A4XX_SP_VS_OUT() argument
1086 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } REG_A4XX_SP_VS_OUT_REG() argument
1112 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } REG_A4XX_SP_VS_VPC_DST() argument
1114 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } REG_A4XX_SP_VS_VPC_DST_REG() argument
1240 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } REG_A4XX_SP_FS_MRT() argument
1242 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } REG_A4XX_SP_FS_MRT_REG() argument
1345 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } REG_A4XX_VPC_VARYING_INTERP() argument
1347 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } REG_A4XX_VPC_VARYING_INTERP_MODE() argument
1349 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } REG_A4XX_VPC_VARYING_PS_REPL() argument
1351 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } REG_A4XX_VPC_VARYING_PS_REPL_MODE() argument
1375 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } REG_A4XX_VSC_PIPE_CONFIG() argument
1377 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } REG_A4XX_VSC_PIPE_CONFIG_REG() argument
1403 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } REG_A4XX_VSC_PIPE_DATA_ADDRESS() argument
1405 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG() argument
1407 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } REG_A4XX_VSC_PIPE_DATA_LENGTH() argument
1409 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } REG_A4XX_VSC_PIPE_DATA_LENGTH_REG() argument
1481 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } REG_A4XX_VFD_FETCH() argument
1483 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } REG_A4XX_VFD_FETCH_INSTR_0() argument
1499 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } REG_A4XX_VFD_FETCH_INSTR_1() argument
1501 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } REG_A4XX_VFD_FETCH_INSTR_2() argument
1509 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } REG_A4XX_VFD_FETCH_INSTR_3() argument
1517 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } REG_A4XX_VFD_DECODE() argument
1519 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } REG_A4XX_VFD_DECODE_INSTR() argument
H A Da3xx.xml.h630 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } REG_A3XX_CP_PROTECT() argument
632 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } REG_A3XX_CP_PROTECT_REG() argument
911 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } REG_A3XX_RB_MRT() argument
913 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } REG_A3XX_RB_MRT_CONTROL() argument
936 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } REG_A3XX_RB_MRT_BUF_INFO() argument
963 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } REG_A3XX_RB_MRT_BUF_BASE() argument
971 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } REG_A3XX_RB_MRT_BLEND_CONTROL() argument
1508 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } REG_A3XX_HLSQ_CL_GLOBAL_WORK() argument
1510 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE() argument
1512 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET() argument
1520 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } REG_A3XX_HLSQ_CL_KERNEL_GROUP() argument
1522 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO() argument
1586 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } REG_A3XX_VFD_FETCH() argument
1588 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } REG_A3XX_VFD_FETCH_INSTR_0() argument
1616 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } REG_A3XX_VFD_FETCH_INSTR_1() argument
1618 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } REG_A3XX_VFD_DECODE() argument
1620 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } REG_A3XX_VFD_DECODE_INSTR() argument
1705 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } REG_A3XX_VPC_VARYING_INTERP() argument
1707 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } REG_A3XX_VPC_VARYING_INTERP_MODE() argument
1805 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } REG_A3XX_VPC_VARYING_PS_REPL() argument
1807 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } REG_A3XX_VPC_VARYING_PS_REPL_MODE() argument
1923 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } REG_A3XX_SP_VS_OUT() argument
1925 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } REG_A3XX_SP_VS_OUT_REG() argument
1951 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } REG_A3XX_SP_VS_VPC_DST() argument
1953 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } REG_A3XX_SP_VS_VPC_DST_REG() argument
2118 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } REG_A3XX_SP_FS_MRT() argument
2120 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } REG_A3XX_SP_FS_MRT_REG() argument
2131 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } REG_A3XX_SP_FS_IMAGE_OUTPUT() argument
2133 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } REG_A3XX_SP_FS_IMAGE_OUTPUT_REG() argument
2285 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } REG_A3XX_VSC_PIPE() argument
2287 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } REG_A3XX_VSC_PIPE_CONFIG() argument
2313 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } REG_A3XX_VSC_PIPE_DATA_ADDRESS() argument
2315 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } REG_A3XX_VSC_PIPE_DATA_LENGTH() argument
2340 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } REG_A3XX_GRAS_CL_USER_PLANE() argument
2342 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } REG_A3XX_GRAS_CL_USER_PLANE_X() argument
2344 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } REG_A3XX_GRAS_CL_USER_PLANE_Y() argument
2346 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } REG_A3XX_GRAS_CL_USER_PLANE_Z() argument
2348 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } REG_A3XX_GRAS_CL_USER_PLANE_W() argument
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/
H A Dmdp5.xml.h184 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); } REG_MDP5_MDP() argument
186 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); } REG_MDP5_MDP_HW_VERSION() argument
206 static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0); } REG_MDP5_MDP_DISP_INTF_SEL() argument
232 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); } REG_MDP5_MDP_INTR_EN() argument
234 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0); } REG_MDP5_MDP_INTR_STATUS() argument
236 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0); } REG_MDP5_MDP_INTR_CLEAR() argument
238 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0); } REG_MDP5_MDP_HIST_INTR_EN() argument
240 static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0); } REG_MDP5_MDP_HIST_INTR_STATUS() argument
242 static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0); } REG_MDP5_MDP_HIST_INTR_CLEAR() argument
244 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); } REG_MDP5_MDP_SPARE_0() argument
247 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_W() argument
249 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_W_REG() argument
269 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_R() argument
271 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_R_REG() argument
301 static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); } REG_MDP5_MDP_IGC() argument
303 static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } REG_MDP5_MDP_IGC_LUT() argument
305 static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } REG_MDP5_MDP_IGC_LUT_REG() argument
342 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } REG_MDP5_CTL() argument
356 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } REG_MDP5_CTL_LAYER() argument
358 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } REG_MDP5_CTL_LAYER_REG() argument
422 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } REG_MDP5_CTL_OP() argument
444 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } REG_MDP5_CTL_FLUSH() argument
475 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } REG_MDP5_CTL_START() argument
477 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } REG_MDP5_CTL_PACK_3D() argument
495 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } REG_MDP5_PIPE() argument
497 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); } REG_MDP5_PIPE_OP_MODE() argument
512 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); } REG_MDP5_PIPE_HIST_CTL_BASE() argument
514 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); } REG_MDP5_PIPE_HIST_LUT_BASE() argument
516 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); } REG_MDP5_PIPE_HIST_LUT_SWAP() argument
518 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); } REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0() argument
532 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); } REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1() argument
546 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); } REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2() argument
560 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); } REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3() argument
574 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); } REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4() argument
582 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
584 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
598 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
600 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
614 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
616 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
624 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
626 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
634 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_SIZE() argument
648 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_IMG_SIZE() argument
662 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_XY() argument
676 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); } REG_MDP5_PIPE_OUT_SIZE() argument
690 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); } REG_MDP5_PIPE_OUT_XY() argument
704 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC0_ADDR() argument
706 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC1_ADDR() argument
708 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC2_ADDR() argument
710 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC3_ADDR() argument
712 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_STRIDE_A() argument
726 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_STRIDE_B() argument
740 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); } REG_MDP5_PIPE_STILE_FRAME_SIZE() argument
742 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_FORMAT() argument
796 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_UNPACK() argument
822 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_OP_MODE() argument
838 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_CONSTANT_COLOR() argument
840 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); } REG_MDP5_PIPE_FETCH_CONFIG() argument
842 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); } REG_MDP5_PIPE_VC1_RANGE() argument
844 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); } REG_MDP5_PIPE_REQPRIO_FIFO_WM_0() argument
846 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); } REG_MDP5_PIPE_REQPRIO_FIFO_WM_1() argument
848 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); } REG_MDP5_PIPE_REQPRIO_FIFO_WM_2() argument
850 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); } REG_MDP5_PIPE_SRC_ADDR_SW_STATUS() argument
852 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); } REG_MDP5_PIPE_CURRENT_SRC0_ADDR() argument
854 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); } REG_MDP5_PIPE_CURRENT_SRC1_ADDR() argument
856 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); } REG_MDP5_PIPE_CURRENT_SRC2_ADDR() argument
858 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); } REG_MDP5_PIPE_CURRENT_SRC3_ADDR() argument
860 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); } REG_MDP5_PIPE_DECIMATION() argument
874 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); } REG_MDP5_PIPE_SCALE_CONFIG() argument
914 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); } REG_MDP5_PIPE_SCALE_PHASE_STEP_X() argument
916 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); } REG_MDP5_PIPE_SCALE_PHASE_STEP_Y() argument
918 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); } REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X() argument
920 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); } REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y() argument
922 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); } REG_MDP5_PIPE_SCALE_INIT_PHASE_X() argument
924 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); } REG_MDP5_PIPE_SCALE_INIT_PHASE_Y() argument
938 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } REG_MDP5_LM() argument
940 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } REG_MDP5_LM_BLEND_COLOR_OUT() argument
946 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } REG_MDP5_LM_OUT_SIZE() argument
960 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); } REG_MDP5_LM_BORDER_COLOR_0() argument
962 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); } REG_MDP5_LM_BORDER_COLOR_1() argument
964 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND() argument
966 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_OP_MODE() argument
988 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_FG_ALPHA() argument
990 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_BG_ALPHA() argument
992 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
994 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
996 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
998 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1000 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1002 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1004 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1006 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; } REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1008 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_IMG_SIZE() argument
1022 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_SIZE() argument
1036 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_XY() argument
1050 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); } REG_MDP5_LM_CURSOR_STRIDE() argument
1058 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); } REG_MDP5_LM_CURSOR_FORMAT() argument
1066 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_BASE_ADDR() argument
1068 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_START_XY() argument
1082 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_BLEND_CONFIG() argument
1092 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); } REG_MDP5_LM_CURSOR_BLEND_PARAM() argument
1094 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0() argument
1096 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1() argument
1098 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); } REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0() argument
1100 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); } REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1() argument
1102 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } REG_MDP5_LM_GC_LUT_BASE() argument
1114 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } REG_MDP5_DSPP() argument
1116 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } REG_MDP5_DSPP_OP_MODE() argument
1133 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); } REG_MDP5_DSPP_PCC_BASE() argument
1135 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); } REG_MDP5_DSPP_DITHER_DEPTH() argument
1137 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); } REG_MDP5_DSPP_HIST_CTL_BASE() argument
1139 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); } REG_MDP5_DSPP_HIST_LUT_BASE() argument
1141 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); } REG_MDP5_DSPP_HIST_LUT_SWAP() argument
1143 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } REG_MDP5_DSPP_PA_BASE() argument
1145 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); } REG_MDP5_DSPP_GAMUT_BASE() argument
1147 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } REG_MDP5_DSPP_GC_BASE() argument
1159 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } REG_MDP5_PP() argument
1161 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } REG_MDP5_PP_TEAR_CHECK_EN() argument
1163 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); } REG_MDP5_PP_SYNC_CONFIG_VSYNC() argument
1173 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); } REG_MDP5_PP_SYNC_CONFIG_HEIGHT() argument
1175 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); } REG_MDP5_PP_SYNC_WRCOUNT() argument
1189 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); } REG_MDP5_PP_VSYNC_INIT_VAL() argument
1191 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); } REG_MDP5_PP_INT_COUNT_VAL() argument
1205 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); } REG_MDP5_PP_SYNC_THRESH() argument
1219 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); } REG_MDP5_PP_START_POS() argument
1221 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); } REG_MDP5_PP_RD_PTR_IRQ() argument
1223 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); } REG_MDP5_PP_WR_PTR_IRQ() argument
1225 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); } REG_MDP5_PP_OUT_LINE_COUNT() argument
1227 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); } REG_MDP5_PP_PP_LINE_COUNT() argument
1229 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); } REG_MDP5_PP_AUTOREFRESH_CONFIG() argument
1231 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); } REG_MDP5_PP_FBC_MODE() argument
1233 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); } REG_MDP5_PP_FBC_BUDGET_CTL() argument
1235 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); } REG_MDP5_PP_FBC_LOSSY_MODE() argument
1248 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } REG_MDP5_INTF() argument
1250 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } REG_MDP5_INTF_TIMING_ENGINE_EN() argument
1252 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } REG_MDP5_INTF_CONFIG() argument
1254 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); } REG_MDP5_INTF_HSYNC_CTL() argument
1268 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); } REG_MDP5_INTF_VSYNC_PERIOD_F0() argument
1270 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); } REG_MDP5_INTF_VSYNC_PERIOD_F1() argument
1272 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); } REG_MDP5_INTF_VSYNC_LEN_F0() argument
1274 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); } REG_MDP5_INTF_VSYNC_LEN_F1() argument
1276 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); } REG_MDP5_INTF_DISPLAY_VSTART_F0() argument
1278 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); } REG_MDP5_INTF_DISPLAY_VSTART_F1() argument
1280 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); } REG_MDP5_INTF_DISPLAY_VEND_F0() argument
1282 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); } REG_MDP5_INTF_DISPLAY_VEND_F1() argument
1284 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); } REG_MDP5_INTF_ACTIVE_VSTART_F0() argument
1293 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); } REG_MDP5_INTF_ACTIVE_VSTART_F1() argument
1301 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); } REG_MDP5_INTF_ACTIVE_VEND_F0() argument
1303 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); } REG_MDP5_INTF_ACTIVE_VEND_F1() argument
1305 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); } REG_MDP5_INTF_DISPLAY_HCTL() argument
1319 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); } REG_MDP5_INTF_ACTIVE_HCTL() argument
1334 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); } REG_MDP5_INTF_BORDER_COLOR() argument
1336 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); } REG_MDP5_INTF_UNDERFLOW_COLOR() argument
1338 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); } REG_MDP5_INTF_HSYNC_SKEW() argument
1340 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); } REG_MDP5_INTF_POLARITY_CTL() argument
1345 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); } REG_MDP5_INTF_TEST_CTL() argument
1347 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); } REG_MDP5_INTF_TP_COLOR0() argument
1349 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); } REG_MDP5_INTF_TP_COLOR1() argument
1351 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); } REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN() argument
1353 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); } REG_MDP5_INTF_PANEL_FORMAT() argument
1355 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); } REG_MDP5_INTF_FRAME_LINE_COUNT_EN() argument
1357 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); } REG_MDP5_INTF_FRAME_COUNT() argument
1359 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); } REG_MDP5_INTF_LINE_COUNT() argument
1361 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); } REG_MDP5_INTF_DEFLICKER_CONFIG() argument
1363 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); } REG_MDP5_INTF_DEFLICKER_STRNG_COEFF() argument
1365 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); } REG_MDP5_INTF_DEFLICKER_WEAK_COEFF() argument
1367 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); } REG_MDP5_INTF_TPG_ENABLE() argument
1369 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); } REG_MDP5_INTF_TPG_MAIN_CONTROL() argument
1371 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); } REG_MDP5_INTF_TPG_VIDEO_CONFIG() argument
1373 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); } REG_MDP5_INTF_TPG_COMPONENT_LIMITS() argument
1375 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); } REG_MDP5_INTF_TPG_RECTANGLE() argument
1377 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); } REG_MDP5_INTF_TPG_INITIAL_VALUE() argument
1379 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); } REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME() argument
1381 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); } REG_MDP5_INTF_TPG_RGB_MAPPING() argument
1391 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } REG_MDP5_AD() argument
1393 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } REG_MDP5_AD_BYPASS() argument
1395 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } REG_MDP5_AD_CTRL_0() argument
1397 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } REG_MDP5_AD_CTRL_1() argument
1399 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } REG_MDP5_AD_FRAME_SIZE() argument
1401 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } REG_MDP5_AD_CON_CTRL_0() argument
1403 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } REG_MDP5_AD_CON_CTRL_1() argument
1405 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } REG_MDP5_AD_STR_MAN() argument
1407 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } REG_MDP5_AD_VAR() argument
1409 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } REG_MDP5_AD_DITH() argument
1411 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } REG_MDP5_AD_DITH_CTRL() argument
1413 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } REG_MDP5_AD_AMP_LIM() argument
1415 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } REG_MDP5_AD_SLOPE() argument
1417 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } REG_MDP5_AD_BW_LVL() argument
1419 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } REG_MDP5_AD_LOGO_POS() argument
1421 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } REG_MDP5_AD_LUT_FI() argument
1423 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } REG_MDP5_AD_LUT_CC() argument
1425 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } REG_MDP5_AD_STR_LIM() argument
1427 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } REG_MDP5_AD_CALIB_AB() argument
1429 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } REG_MDP5_AD_CALIB_CD() argument
1431 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } REG_MDP5_AD_MODE_SEL() argument
1433 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } REG_MDP5_AD_TFILT_CTRL() argument
1435 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } REG_MDP5_AD_BL_MINMAX() argument
1437 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } REG_MDP5_AD_BL() argument
1439 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } REG_MDP5_AD_BL_MAX() argument
1441 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } REG_MDP5_AD_AL() argument
1443 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } REG_MDP5_AD_AL_MIN() argument
1445 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } REG_MDP5_AD_AL_FILT() argument
1447 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } REG_MDP5_AD_CFG_BUF() argument
1449 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } REG_MDP5_AD_LUT_AL() argument
1451 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } REG_MDP5_AD_TARG_STR() argument
1453 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } REG_MDP5_AD_START_CALC() argument
1455 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } REG_MDP5_AD_STR_OUT() argument
1457 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } REG_MDP5_AD_BL_OUT() argument
1459 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } argument

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