Lines Matching refs:BIT
137 #define FLASH_STATUS_FLASH_ON BIT(3)
138 #define FLASH_STATUS_TORCH_ON BIT(2)
141 #define FLASH_INT_FLED2_OPEN BIT(0)
142 #define FLASH_INT_FLED2_SHORT BIT(1)
143 #define FLASH_INT_FLED1_OPEN BIT(2)
144 #define FLASH_INT_FLED1_SHORT BIT(3)
145 #define FLASH_INT_OVER_CURRENT BIT(4)
170 #define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT)
171 #define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT)
172 #define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT)
173 #define CHG_INT_OK_CHGIN_MASK BIT(CHG_INT_OK_CHGIN_SHIFT)
174 #define CHG_INT_OK_DETBAT_MASK BIT(CHG_INT_OK_DETBAT_SHIFT)
186 #define CHG_DETAILS_01_TREG_MASK BIT(7)
231 #define CHG_CNFG_01_PQEN_MAKS BIT(CHG_CNFG_01_PQEN_SHIFT)
318 #define MAX77693_STATUS1_ADCLOW_MASK BIT(MAX77693_STATUS1_ADCLOW_SHIFT)
319 #define MAX77693_STATUS1_ADCERR_MASK BIT(MAX77693_STATUS1_ADCERR_SHIFT)
320 #define MAX77693_STATUS1_ADC1K_MASK BIT(MAX77693_STATUS1_ADC1K_SHIFT)
329 #define MAX77693_STATUS2_CHGDETRUN_MASK BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT)
330 #define MAX77693_STATUS2_DCDTMR_MASK BIT(MAX77693_STATUS2_DCDTMR_SHIFT)
331 #define MAX77693_STATUS2_DXOVP_MASK BIT(MAX77693_STATUS2_DXOVP_SHIFT)
332 #define MAX77693_STATUS2_VBVOLT_MASK BIT(MAX77693_STATUS2_VBVOLT_SHIFT)
333 #define MAX77693_STATUS2_VIDRM_MASK BIT(MAX77693_STATUS2_VIDRM_SHIFT)
336 #define MAX77693_STATUS3_OVP_MASK BIT(MAX77693_STATUS3_OVP_SHIFT)
382 #define MAX77693_CONTROL2_LOWPWR_MASK BIT(MAX77693_CONTROL2_LOWPWR_SHIFT)
383 #define MAX77693_CONTROL2_ADCEN_MASK BIT(MAX77693_CONTROL2_ADCEN_SHIFT)
384 #define MAX77693_CONTROL2_CPEN_MASK BIT(MAX77693_CONTROL2_CPEN_SHIFT)
385 #define MAX77693_CONTROL2_SFOUTASRT_MASK BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT)
386 #define MAX77693_CONTROL2_SFOUTORD_MASK BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT)
387 #define MAX77693_CONTROL2_ACCDET_MASK BIT(MAX77693_CONTROL2_ACCDET_SHIFT)
388 #define MAX77693_CONTROL2_USBCPINT_MASK BIT(MAX77693_CONTROL2_USBCPINT_SHIFT)
389 #define MAX77693_CONTROL2_RCPS_MASK BIT(MAX77693_CONTROL2_RCPS_SHIFT)
441 #define SRC_IRQ_CHARGER BIT(0)
442 #define SRC_IRQ_TOP BIT(1)
443 #define SRC_IRQ_FLASH BIT(2)
444 #define SRC_IRQ_MUIC BIT(3)
448 #define LED_IRQ_FLED2_OPEN BIT(0)
449 #define LED_IRQ_FLED2_SHORT BIT(1)
450 #define LED_IRQ_FLED1_OPEN BIT(2)
451 #define LED_IRQ_FLED1_SHORT BIT(3)
452 #define LED_IRQ_MAX_FLASH BIT(4)
454 #define TOPSYS_IRQ_T120C_INT BIT(0)
455 #define TOPSYS_IRQ_T140C_INT BIT(1)
456 #define TOPSYS_IRQ_LOWSYS_INT BIT(3)
458 #define CHG_IRQ_BYP_I BIT(0)
459 #define CHG_IRQ_THM_I BIT(2)
460 #define CHG_IRQ_BAT_I BIT(3)
461 #define CHG_IRQ_CHG_I BIT(4)
462 #define CHG_IRQ_CHGIN_I BIT(6)
464 #define MUIC_IRQ_INT1_ADC BIT(0)
465 #define MUIC_IRQ_INT1_ADC_LOW BIT(1)
466 #define MUIC_IRQ_INT1_ADC_ERR BIT(2)
467 #define MUIC_IRQ_INT1_ADC1K BIT(3)
469 #define MUIC_IRQ_INT2_CHGTYP BIT(0)
470 #define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
471 #define MUIC_IRQ_INT2_DCDTMR BIT(2)
472 #define MUIC_IRQ_INT2_DXOVP BIT(3)
473 #define MUIC_IRQ_INT2_VBVOLT BIT(4)
474 #define MUIC_IRQ_INT2_VIDRM BIT(5)
476 #define MUIC_IRQ_INT3_EOC BIT(0)
477 #define MUIC_IRQ_INT3_CGMBC BIT(1)
478 #define MUIC_IRQ_INT3_OVP BIT(2)
479 #define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
480 #define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
481 #define MUIC_IRQ_INT3_BAT_DET BIT(5)