81 static void msm_handle_tx(struct uart_port *port);
84 void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)  in msm_stop_dma()  argument
86 	struct device *dev = port->dev;  in msm_stop_dma()
102 	val = msm_read(port, UARTDM_DMEN);  in msm_stop_dma()
104 	msm_write(port, val, UARTDM_DMEN);  in msm_stop_dma()
223 static inline void msm_wait_for_xmitr(struct uart_port *port)  in msm_wait_for_xmitr()  argument
225 	while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {  in msm_wait_for_xmitr()
226 		if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)  in msm_wait_for_xmitr()
230 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in msm_wait_for_xmitr()
233 static void msm_stop_tx(struct uart_port *port)  in msm_stop_tx()  argument
235 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_stop_tx()
238 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_tx()
241 static void msm_start_tx(struct uart_port *port)  in msm_start_tx()  argument
243 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_start_tx()
251 	msm_write(port, msm_port->imr, UART_IMR);  in msm_start_tx()
254 static void msm_reset_dm_count(struct uart_port *port, int count)  in msm_reset_dm_count()  argument
256 	msm_wait_for_xmitr(port);  in msm_reset_dm_count()
257 	msm_write(port, count, UARTDM_NCF_TX);  in msm_reset_dm_count()
258 	msm_read(port, UARTDM_NCF_TX);  in msm_reset_dm_count()
264 	struct uart_port *port = &msm_port->uart;  in msm_complete_tx_dma()  local
265 	struct circ_buf *xmit = &port->state->xmit;  in msm_complete_tx_dma()
273 	spin_lock_irqsave(&port->lock, flags);  in msm_complete_tx_dma()
281 	dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);  in msm_complete_tx_dma()
283 	val = msm_read(port, UARTDM_DMEN);  in msm_complete_tx_dma()
285 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_tx_dma()
288 		msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_complete_tx_dma()
289 		msm_write(port, UART_CR_TX_ENABLE, UART_CR);  in msm_complete_tx_dma()
293 	port->icount.tx += count;  in msm_complete_tx_dma()
301 	msm_write(port, msm_port->imr, UART_IMR);  in msm_complete_tx_dma()
304 		uart_write_wakeup(port);  in msm_complete_tx_dma()
306 	msm_handle_tx(port);  in msm_complete_tx_dma()
308 	spin_unlock_irqrestore(&port->lock, flags);  in msm_complete_tx_dma()
314 	struct uart_port *port = &msm_port->uart;  in msm_handle_tx_dma()  local
322 	dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);  in msm_handle_tx_dma()
323 	ret = dma_mapping_error(port->dev, dma->phys);  in msm_handle_tx_dma()
349 	msm_write(port, msm_port->imr, UART_IMR);  in msm_handle_tx_dma()
353 	val = msm_read(port, UARTDM_DMEN);  in msm_handle_tx_dma()
357 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
359 	msm_reset_dm_count(port, count);  in msm_handle_tx_dma()
362 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
367 	dma_unmap_single(port->dev, dma->phys, count, dma->dir);  in msm_handle_tx_dma()
374 	struct uart_port *port = &msm_port->uart;  in msm_complete_rx_dma()  local
375 	struct tty_port *tport = &port->state->port;  in msm_complete_rx_dma()
381 	spin_lock_irqsave(&port->lock, flags);  in msm_complete_rx_dma()
387 	val = msm_read(port, UARTDM_DMEN);  in msm_complete_rx_dma()
389 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_rx_dma()
393 	msm_write(port, msm_port->imr, UART_IMR);  in msm_complete_rx_dma()
395 	if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {  in msm_complete_rx_dma()
396 		port->icount.overrun++;  in msm_complete_rx_dma()
398 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_complete_rx_dma()
401 	count = msm_read(port, UARTDM_RX_TOTAL_SNAP);  in msm_complete_rx_dma()
403 	port->icount.rx += count;  in msm_complete_rx_dma()
407 	dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);  in msm_complete_rx_dma()
413 			port->icount.brk++;  in msm_complete_rx_dma()
416 			if (uart_handle_break(port))  in msm_complete_rx_dma()
420 		if (!(port->read_status_mask & UART_SR_RX_BREAK))  in msm_complete_rx_dma()
423 		spin_unlock_irqrestore(&port->lock, flags);  in msm_complete_rx_dma()
424 		sysrq = uart_handle_sysrq_char(port, dma->virt[i]);  in msm_complete_rx_dma()
425 		spin_lock_irqsave(&port->lock, flags);  in msm_complete_rx_dma()
432 	spin_unlock_irqrestore(&port->lock, flags);  in msm_complete_rx_dma()
505 static void msm_stop_rx(struct uart_port *port)  in msm_stop_rx()  argument
507 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_stop_rx()
511 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_rx()
514 		msm_stop_dma(port, dma);  in msm_stop_rx()
517 static void msm_enable_ms(struct uart_port *port)  in msm_enable_ms()  argument
519 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_enable_ms()
522 	msm_write(port, msm_port->imr, UART_IMR);  in msm_enable_ms()
525 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)  in msm_handle_rx_dm()  argument
527 	struct tty_port *tport = &port->state->port;  in msm_handle_rx_dm()
530 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_handle_rx_dm()
532 	if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {  in msm_handle_rx_dm()
533 		port->icount.overrun++;  in msm_handle_rx_dm()
535 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx_dm()
539 		count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -  in msm_handle_rx_dm()
543 		count = 4 * (msm_read(port, UART_RFWR));  in msm_handle_rx_dm()
549 	port->icount.rx += count;  in msm_handle_rx_dm()
555 		sr = msm_read(port, UART_SR);  in msm_handle_rx_dm()
561 		ioread32_rep(port->membase + UARTDM_RF, buf, 1);  in msm_handle_rx_dm()
568 				port->icount.brk++;  in msm_handle_rx_dm()
571 				if (uart_handle_break(port))  in msm_handle_rx_dm()
575 			if (!(port->read_status_mask & UART_SR_RX_BREAK))  in msm_handle_rx_dm()
578 			spin_unlock(&port->lock);  in msm_handle_rx_dm()
579 			sysrq = uart_handle_sysrq_char(port, buf[i]);  in msm_handle_rx_dm()
580 			spin_lock(&port->lock);  in msm_handle_rx_dm()
587 	spin_unlock(&port->lock);  in msm_handle_rx_dm()
589 	spin_lock(&port->lock);  in msm_handle_rx_dm()
592 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_handle_rx_dm()
593 	msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_handle_rx_dm()
594 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_handle_rx_dm()
600 static void msm_handle_rx(struct uart_port *port)  in msm_handle_rx()  argument
602 	struct tty_port *tport = &port->state->port;  in msm_handle_rx()
609 	if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {  in msm_handle_rx()
610 		port->icount.overrun++;  in msm_handle_rx()
612 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx()
616 	while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {  in msm_handle_rx()
621 		c = msm_read(port, UART_RF);  in msm_handle_rx()
624 			port->icount.brk++;  in msm_handle_rx()
625 			if (uart_handle_break(port))  in msm_handle_rx()
628 			port->icount.frame++;  in msm_handle_rx()
630 			port->icount.rx++;  in msm_handle_rx()
634 		sr &= port->read_status_mask;  in msm_handle_rx()
641 		spin_unlock(&port->lock);  in msm_handle_rx()
642 		sysrq = uart_handle_sysrq_char(port, c);  in msm_handle_rx()
643 		spin_lock(&port->lock);  in msm_handle_rx()
648 	spin_unlock(&port->lock);  in msm_handle_rx()
650 	spin_lock(&port->lock);  in msm_handle_rx()
653 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)  in msm_handle_tx_pio()  argument
655 	struct circ_buf *xmit = &port->state->xmit;  in msm_handle_tx_pio()
656 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_handle_tx_pio()
662 		tf = port->membase + UARTDM_TF;  in msm_handle_tx_pio()
664 		tf = port->membase + UART_TF;  in msm_handle_tx_pio()
667 		msm_reset_dm_count(port, tx_count);  in msm_handle_tx_pio()
673 		if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))  in msm_handle_tx_pio()
684 			port->icount.tx++;  in msm_handle_tx_pio()
694 		msm_stop_tx(port);  in msm_handle_tx_pio()
697 		uart_write_wakeup(port);  in msm_handle_tx_pio()
700 static void msm_handle_tx(struct uart_port *port)  in msm_handle_tx()  argument
702 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_handle_tx()
709 	if (port->x_char) {  in msm_handle_tx()
711 			tf = port->membase + UARTDM_TF;  in msm_handle_tx()
713 			tf = port->membase + UART_TF;  in msm_handle_tx()
716 			msm_reset_dm_count(port, 1);  in msm_handle_tx()
718 		iowrite8_rep(tf, &port->x_char, 1);  in msm_handle_tx()
719 		port->icount.tx++;  in msm_handle_tx()
720 		port->x_char = 0;  in msm_handle_tx()
724 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {  in msm_handle_tx()
725 		msm_stop_tx(port);  in msm_handle_tx()
741 	if (pio_count > port->fifosize)  in msm_handle_tx()
742 		pio_count = port->fifosize;  in msm_handle_tx()
745 		msm_handle_tx_pio(port, pio_count);  in msm_handle_tx()
750 		msm_handle_tx_pio(port, pio_count);  in msm_handle_tx()
753 static void msm_handle_delta_cts(struct uart_port *port)  in msm_handle_delta_cts()  argument
755 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_handle_delta_cts()
756 	port->icount.cts++;  in msm_handle_delta_cts()
757 	wake_up_interruptible(&port->state->port.delta_msr_wait);  in msm_handle_delta_cts()
762 	struct uart_port *port = dev_id;  in msm_uart_irq()  local
763 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_uart_irq()
769 	spin_lock_irqsave(&port->lock, flags);  in msm_uart_irq()
770 	misr = msm_read(port, UART_MISR);  in msm_uart_irq()
771 	msm_write(port, 0, UART_IMR); /* disable interrupt */  in msm_uart_irq()
775 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_uart_irq()
781 			msm_write(port, val, UART_CR);  in msm_uart_irq()
783 			msm_write(port, val, UART_CR);  in msm_uart_irq()
790 			msm_handle_rx_dm(port, misr);  in msm_uart_irq()
792 			msm_handle_rx(port);  in msm_uart_irq()
796 		msm_handle_tx(port);  in msm_uart_irq()
798 		msm_handle_delta_cts(port);  in msm_uart_irq()
800 	msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */  in msm_uart_irq()
801 	spin_unlock_irqrestore(&port->lock, flags);  in msm_uart_irq()
806 static unsigned int msm_tx_empty(struct uart_port *port)  in msm_tx_empty()  argument
808 	return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;  in msm_tx_empty()
811 static unsigned int msm_get_mctrl(struct uart_port *port)  in msm_get_mctrl()  argument
816 static void msm_reset(struct uart_port *port)  in msm_reset()  argument
818 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_reset()
821 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
822 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
823 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
824 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
825 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
826 	msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);  in msm_reset()
830 		msm_write(port, 0, UARTDM_DMEN);  in msm_reset()
833 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)  in msm_set_mctrl()  argument
837 	mr = msm_read(port, UART_MR1);  in msm_set_mctrl()
841 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
842 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
845 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
849 static void msm_break_ctl(struct uart_port *port, int break_ctl)  in msm_break_ctl()  argument
852 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
854 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
864 msm_find_best_baud(struct uart_port *port, unsigned int baud)  in msm_find_best_baud()  argument
888 	divisor = uart_get_divisor(port, baud);  in msm_find_best_baud()
897 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,  in msm_set_baud_rate()  argument
901 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_set_baud_rate()
905 	entry = msm_find_best_baud(port, baud);  in msm_set_baud_rate()
907 	msm_write(port, entry->code, UART_CSR);  in msm_set_baud_rate()
910 		port->uartclk = baud * 16;  in msm_set_baud_rate()
913 	spin_unlock_irqrestore(&port->lock, flags);  in msm_set_baud_rate()
915 	clk_set_rate(msm_port->clk, port->uartclk);  in msm_set_baud_rate()
917 	spin_lock_irqsave(&port->lock, flags);  in msm_set_baud_rate()
932 	msm_write(port, watermark, UART_IPR);  in msm_set_baud_rate()
935 	watermark = (port->fifosize * 3) / 4;  in msm_set_baud_rate()
936 	msm_write(port, watermark, UART_RFWR);  in msm_set_baud_rate()
939 	msm_write(port, 10, UART_TFWR);  in msm_set_baud_rate()
941 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
942 	msm_reset(port);  in msm_set_baud_rate()
945 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
951 	msm_write(port, msm_port->imr, UART_IMR);  in msm_set_baud_rate()
954 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
955 		msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_set_baud_rate()
956 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
962 static void msm_init_clock(struct uart_port *port)  in msm_init_clock()  argument
964 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_init_clock()
968 	msm_serial_set_mnd_regs(port);  in msm_init_clock()
971 static int msm_startup(struct uart_port *port)  in msm_startup()  argument
973 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_startup()
978 		 "msm_serial%d", port->line);  in msm_startup()
980 	ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,  in msm_startup()
981 			  msm_port->name, port);  in msm_startup()
985 	msm_init_clock(port);  in msm_startup()
987 	if (likely(port->fifosize > 12))  in msm_startup()
988 		rfr_level = port->fifosize - 12;  in msm_startup()
990 		rfr_level = port->fifosize;  in msm_startup()
993 	data = msm_read(port, UART_MR1);  in msm_startup()
1004 	msm_write(port, data, UART_MR1);  in msm_startup()
1014 static void msm_shutdown(struct uart_port *port)  in msm_shutdown()  argument
1016 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_shutdown()
1019 	msm_write(port, 0, UART_IMR); /* disable interrupts */  in msm_shutdown()
1026 	free_irq(port->irq, port);  in msm_shutdown()
1029 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,  in msm_set_termios()  argument
1032 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_set_termios()
1037 	spin_lock_irqsave(&port->lock, flags);  in msm_set_termios()
1040 		msm_stop_dma(port, dma);  in msm_set_termios()
1043 	baud = uart_get_baud_rate(port, termios, old, 300, 4000000);  in msm_set_termios()
1044 	baud = msm_set_baud_rate(port, baud, &flags);  in msm_set_termios()
1049 	mr = msm_read(port, UART_MR2);  in msm_set_termios()
1086 	msm_write(port, mr, UART_MR2);  in msm_set_termios()
1089 	mr = msm_read(port, UART_MR1);  in msm_set_termios()
1095 	msm_write(port, mr, UART_MR1);  in msm_set_termios()
1098 	port->read_status_mask = 0;  in msm_set_termios()
1100 		port->read_status_mask |= UART_SR_PAR_FRAME_ERR;  in msm_set_termios()
1102 		port->read_status_mask |= UART_SR_RX_BREAK;  in msm_set_termios()
1104 	uart_update_timeout(port, termios->c_cflag, baud);  in msm_set_termios()
1109 	spin_unlock_irqrestore(&port->lock, flags);  in msm_set_termios()
1112 static const char *msm_type(struct uart_port *port)  in msm_type()  argument
1117 static void msm_release_port(struct uart_port *port)  in msm_release_port()  argument
1119 	struct platform_device *pdev = to_platform_device(port->dev);  in msm_release_port()
1128 	release_mem_region(port->mapbase, size);  in msm_release_port()
1129 	iounmap(port->membase);  in msm_release_port()
1130 	port->membase = NULL;  in msm_release_port()
1133 static int msm_request_port(struct uart_port *port)  in msm_request_port()  argument
1135 	struct platform_device *pdev = to_platform_device(port->dev);  in msm_request_port()
1146 	if (!request_mem_region(port->mapbase, size, "msm_serial"))  in msm_request_port()
1149 	port->membase = ioremap(port->mapbase, size);  in msm_request_port()
1150 	if (!port->membase) {  in msm_request_port()
1158 	release_mem_region(port->mapbase, size);  in msm_request_port()
1162 static void msm_config_port(struct uart_port *port, int flags)  in msm_config_port()  argument
1167 		port->type = PORT_MSM;  in msm_config_port()
1168 		ret = msm_request_port(port);  in msm_config_port()
1174 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)  in msm_verify_port()  argument
1178 	if (unlikely(port->irq != ser->irq))  in msm_verify_port()
1183 static void msm_power(struct uart_port *port, unsigned int state,  in msm_power()  argument
1186 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_power()
1203 static int msm_poll_get_char_single(struct uart_port *port)  in msm_poll_get_char_single()  argument
1205 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_poll_get_char_single()
1208 	if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))  in msm_poll_get_char_single()
1211 	return msm_read(port, rf_reg) & 0xff;  in msm_poll_get_char_single()
1214 static int msm_poll_get_char_dm(struct uart_port *port)  in msm_poll_get_char_dm()  argument
1226 	} else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {  in msm_poll_get_char_dm()
1231 		count = msm_read(port, UARTDM_RXFS);  in msm_poll_get_char_dm()
1234 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
1235 			slop = msm_read(port, UARTDM_RF);  in msm_poll_get_char_dm()
1238 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
1239 			msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_poll_get_char_dm()
1240 			msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,  in msm_poll_get_char_dm()
1247 		slop = msm_read(port, UARTDM_RF);  in msm_poll_get_char_dm()
1255 static int msm_poll_get_char(struct uart_port *port)  in msm_poll_get_char()  argument
1259 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_poll_get_char()
1262 	imr = msm_read(port, UART_IMR);  in msm_poll_get_char()
1263 	msm_write(port, 0, UART_IMR);  in msm_poll_get_char()
1266 		c = msm_poll_get_char_dm(port);  in msm_poll_get_char()
1268 		c = msm_poll_get_char_single(port);  in msm_poll_get_char()
1271 	msm_write(port, imr, UART_IMR);  in msm_poll_get_char()
1276 static void msm_poll_put_char(struct uart_port *port, unsigned char c)  in msm_poll_put_char()  argument
1279 	struct msm_port *msm_port = UART_TO_MSM(port);  in msm_poll_put_char()
1282 	imr = msm_read(port, UART_IMR);  in msm_poll_put_char()
1283 	msm_write(port, 0, UART_IMR);  in msm_poll_put_char()
1286 		msm_reset_dm_count(port, 1);  in msm_poll_put_char()
1289 	while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))  in msm_poll_put_char()
1293 	msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);  in msm_poll_put_char()
1296 	while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))  in msm_poll_put_char()
1300 	msm_write(port, imr, UART_IMR);  in msm_poll_put_char()
1366 static void __msm_console_write(struct uart_port *port, const char *s,  in __msm_console_write()  argument
1375 		tf = port->membase + UARTDM_TF;  in __msm_console_write()
1377 		tf = port->membase + UART_TF;  in __msm_console_write()
1385 	spin_lock(&port->lock);  in __msm_console_write()
1387 		msm_reset_dm_count(port, count);  in __msm_console_write()
1415 		while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))  in __msm_console_write()
1421 	spin_unlock(&port->lock);  in __msm_console_write()
1427 	struct uart_port *port;  in msm_console_write()  local
1432 	port = msm_get_port_from_line(co->index);  in msm_console_write()
1433 	msm_port = UART_TO_MSM(port);  in msm_console_write()
1435 	__msm_console_write(port, s, count, msm_port->is_uartdm);  in msm_console_write()
1440 	struct uart_port *port;  in msm_console_setup()  local
1449 	port = msm_get_port_from_line(co->index);  in msm_console_setup()
1451 	if (unlikely(!port->membase))  in msm_console_setup()
1454 	msm_init_clock(port);  in msm_console_setup()
1459 	pr_info("msm_serial: console setup on port #%d\n", port->line);  in msm_console_setup()
1461 	return uart_set_options(port, co, baud, parity, bits, flow);  in msm_console_setup()
1469 	__msm_console_write(&dev->port, s, n, false);  in msm_serial_early_write()
1475 	if (!device->port.membase)  in msm_serial_early_console_setup()
1490 	__msm_console_write(&dev->port, s, n, true);  in msm_serial_early_write_dm()
1497 	if (!device->port.membase)  in msm_serial_early_console_setup_dm()
1547 	struct uart_port *port;  in msm_serial_probe()  local
1564 	port = msm_get_port_from_line(line);  in msm_serial_probe()
1565 	port->dev = &pdev->dev;  in msm_serial_probe()
1566 	msm_port = UART_TO_MSM(port);  in msm_serial_probe()
1586 	port->uartclk = clk_get_rate(msm_port->clk);  in msm_serial_probe()
1587 	dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);  in msm_serial_probe()
1592 	port->mapbase = resource->start;  in msm_serial_probe()
1597 	port->irq = irq;  in msm_serial_probe()
1599 	platform_set_drvdata(pdev, port);  in msm_serial_probe()
1601 	return uart_add_one_port(&msm_uart_driver, port);  in msm_serial_probe()
1606 	struct uart_port *port = platform_get_drvdata(pdev);  in msm_serial_remove()  local
1608 	uart_remove_one_port(&msm_uart_driver, port);  in msm_serial_remove()