104 	msm_write(port, val, UARTDM_DMEN);  in msm_stop_dma()
230 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in msm_wait_for_xmitr()
238 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_tx()
251 	msm_write(port, msm_port->imr, UART_IMR);  in msm_start_tx()
257 	msm_write(port, count, UARTDM_NCF_TX);  in msm_reset_dm_count()
285 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_tx_dma()
288 		msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_complete_tx_dma()
289 		msm_write(port, UART_CR_TX_ENABLE, UART_CR);  in msm_complete_tx_dma()
301 	msm_write(port, msm_port->imr, UART_IMR);  in msm_complete_tx_dma()
349 	msm_write(port, msm_port->imr, UART_IMR);  in msm_handle_tx_dma()
357 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
362 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
389 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_rx_dma()
393 	msm_write(port, msm_port->imr, UART_IMR);  in msm_complete_rx_dma()
398 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_complete_rx_dma()
480 	msm_write(uart, msm_port->imr, UART_IMR);  in msm_start_rx_dma()
486 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
487 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
493 		msm_write(uart, val, UARTDM_DMEN);  in msm_start_rx_dma()
495 	msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);  in msm_start_rx_dma()
498 		msm_write(uart, val, UARTDM_DMEN);  in msm_start_rx_dma()
511 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_rx()
522 	msm_write(port, msm_port->imr, UART_IMR);  in msm_enable_ms()
535 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx_dm()
592 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_handle_rx_dm()
593 	msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_handle_rx_dm()
594 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_handle_rx_dm()
612 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx()
755 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_handle_delta_cts()
771 	msm_write(port, 0, UART_IMR); /* disable interrupt */  in msm_uart_irq()
775 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_uart_irq()
781 			msm_write(port, val, UART_CR);  in msm_uart_irq()
783 			msm_write(port, val, UART_CR);  in msm_uart_irq()
800 	msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */  in msm_uart_irq()
821 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
822 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
823 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
824 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
825 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
826 	msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);  in msm_reset()
830 		msm_write(port, 0, UARTDM_DMEN);  in msm_reset()
841 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
842 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
845 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
852 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
854 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
907 	msm_write(port, entry->code, UART_CSR);  in msm_set_baud_rate()
932 	msm_write(port, watermark, UART_IPR);  in msm_set_baud_rate()
936 	msm_write(port, watermark, UART_RFWR);  in msm_set_baud_rate()
939 	msm_write(port, 10, UART_TFWR);  in msm_set_baud_rate()
941 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
945 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
951 	msm_write(port, msm_port->imr, UART_IMR);  in msm_set_baud_rate()
954 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
955 		msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_set_baud_rate()
956 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
1004 	msm_write(port, data, UART_MR1);  in msm_startup()
1019 	msm_write(port, 0, UART_IMR); /* disable interrupts */  in msm_shutdown()
1086 	msm_write(port, mr, UART_MR2);  in msm_set_termios()
1095 	msm_write(port, mr, UART_MR1);  in msm_set_termios()
1234 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
1238 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
1239 			msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_poll_get_char_dm()
1240 			msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,  in msm_poll_get_char_dm()
1263 	msm_write(port, 0, UART_IMR);  in msm_poll_get_char()
1271 	msm_write(port, imr, UART_IMR);  in msm_poll_get_char()
1283 	msm_write(port, 0, UART_IMR);  in msm_poll_put_char()
1293 	msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);  in msm_poll_put_char()
1300 	msm_write(port, imr, UART_IMR);  in msm_poll_put_char()