150 		muxval = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_endisable()
164 			readl(spmx->rsc_virtbase + mux->ctrlreg);  in sirfsoc_pinmux_endisable()
215 	muxval = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_request_gpio()
338 			spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_suspend_noirq()
341 		spmx->ints_regs[i] = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_suspend_noirq()
343 		spmx->paden_regs[i] = readl(spmx->gpio_virtbase +  in sirfsoc_pinmux_suspend_noirq()
346 	spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);  in sirfsoc_pinmux_suspend_noirq()
349 		spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);  in sirfsoc_pinmux_suspend_noirq()
431 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_ack()
449 	val = readl(sgpio->chip.regs + offset);  in __sirfsoc_gpio_irq_mask()
479 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_unmask()
500 	val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_irq_type()
568 	status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));  in sirfsoc_gpio_handle_irq()
578 		ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));  in sirfsoc_gpio_handle_irq()
603 	val = readl(sgpio->chip.regs + ctrl_offset);  in sirfsoc_gpio_set_input()
676 	out_ctrl = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_output()
718 	val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_get_value()
735 	ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));  in sirfsoc_gpio_set_value()
754 			u32 val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pullup()
771 			u32 val = readl(sgpio->chip.regs + offset);  in sirfsoc_gpio_set_pulldown()