Lines Matching refs:offset
220 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) in u300_gpio_get() argument
224 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); in u300_gpio_get()
227 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in u300_gpio_set() argument
235 val = readl(U300_PIN_REG(offset, dor)); in u300_gpio_set()
237 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set()
239 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set()
244 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in u300_gpio_direction_input() argument
251 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input()
253 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); in u300_gpio_direction_input()
254 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input()
259 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in u300_gpio_direction_output() argument
268 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_direction_output()
274 ((offset & 0x07) << 1)); in u300_gpio_direction_output()
278 ((offset & 0x07) << 1)); in u300_gpio_direction_output()
280 << ((offset & 0x07) << 1)); in u300_gpio_direction_output()
281 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_output()
283 u300_gpio_set(chip, offset, value); in u300_gpio_direction_output()
290 unsigned offset, in u300_gpio_config_get() argument
299 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); in u300_gpio_config_get()
302 drmode = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_get()
303 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); in u300_gpio_config_get()
304 drmode >>= ((offset & 0x07) << 1); in u300_gpio_config_get()
348 int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, in u300_gpio_config_set() argument
359 val = readl(U300_PIN_REG(offset, per)); in u300_gpio_config_set()
360 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set()
363 val = readl(U300_PIN_REG(offset, per)); in u300_gpio_config_set()
364 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set()
367 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
369 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
371 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
372 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
375 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
377 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
379 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
380 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
383 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
385 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
387 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
388 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
410 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) in u300_toggle_trigger() argument
414 val = readl(U300_PIN_REG(offset, icr)); in u300_toggle_trigger()
416 if (u300_gpio_get(&gpio->chip, offset)) { in u300_toggle_trigger()
418 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_toggle_trigger()
420 offset); in u300_toggle_trigger()
423 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_toggle_trigger()
425 offset); in u300_toggle_trigger()
434 int offset = d->hwirq; in u300_gpio_irq_type() local
446 offset); in u300_gpio_irq_type()
447 port->toggle_edge_mode |= U300_PIN_BIT(offset); in u300_gpio_irq_type()
448 u300_toggle_trigger(gpio, offset); in u300_gpio_irq_type()
451 offset); in u300_gpio_irq_type()
452 val = readl(U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
453 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
454 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); in u300_gpio_irq_type()
457 offset); in u300_gpio_irq_type()
458 val = readl(U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
459 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
460 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); in u300_gpio_irq_type()
471 int offset = d->hwirq; in u300_gpio_irq_enable() local
476 d->hwirq, port->name, offset); in u300_gpio_irq_enable()
478 val = readl(U300_PIN_REG(offset, ien)); in u300_gpio_irq_enable()
479 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); in u300_gpio_irq_enable()
487 int offset = d->hwirq; in u300_gpio_irq_disable() local
492 val = readl(U300_PIN_REG(offset, ien)); in u300_gpio_irq_disable()
493 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); in u300_gpio_irq_disable()
528 int offset = pinoffset + irqoffset; in u300_gpio_irq_handler() local
529 int pin_irq = irq_find_mapping(chip->irqdomain, offset); in u300_gpio_irq_handler()
532 pin_irq, offset); in u300_gpio_irq_handler()
538 if (port->toggle_edge_mode & U300_PIN_BIT(offset)) in u300_gpio_irq_handler()
539 u300_toggle_trigger(gpio, offset); in u300_gpio_irq_handler()
547 int offset, in u300_gpio_init_pin() argument
552 u300_gpio_direction_output(&gpio->chip, offset, conf->outval); in u300_gpio_init_pin()
555 u300_gpio_config_set(&gpio->chip, offset, in u300_gpio_init_pin()
559 u300_gpio_config_set(&gpio->chip, offset, in u300_gpio_init_pin()
563 offset, conf->outval); in u300_gpio_init_pin()
565 u300_gpio_direction_input(&gpio->chip, offset); in u300_gpio_init_pin()
568 u300_gpio_set(&gpio->chip, offset, 0); in u300_gpio_init_pin()
571 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); in u300_gpio_init_pin()
574 offset, conf->bias_mode); in u300_gpio_init_pin()
586 int offset = (i*8) + j; in u300_gpio_init_coh901571() local
589 u300_gpio_init_pin(gpio, offset, conf); in u300_gpio_init_coh901571()
600 unsigned int offset; member
604 #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
731 p->offset, p->pin_base, 1); in u300_gpio_probe()