Lines Matching refs:pctrl
662 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, in chv_padreg() argument
671 return pctrl->regs + offset + reg; in chv_padreg()
682 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) in chv_pad_locked() argument
686 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); in chv_pad_locked()
692 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_get_groups_count() local
694 return pctrl->community->ngroups; in chv_get_groups_count()
700 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_get_group_name() local
702 return pctrl->community->groups[group].name; in chv_get_group_name()
708 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_get_group_pins() local
710 *pins = pctrl->community->groups[group].pins; in chv_get_group_pins()
711 *npins = pctrl->community->groups[group].npins; in chv_get_group_pins()
718 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_pin_dbg_show() local
723 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_pin_dbg_show()
725 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); in chv_pin_dbg_show()
726 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); in chv_pin_dbg_show()
727 locked = chv_pad_locked(pctrl, offset); in chv_pin_dbg_show()
729 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_pin_dbg_show()
757 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_get_functions_count() local
759 return pctrl->community->nfunctions; in chv_get_functions_count()
765 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_get_function_name() local
767 return pctrl->community->functions[function].name; in chv_get_function_name()
775 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_get_function_groups() local
777 *groups = pctrl->community->functions[function].groups; in chv_get_function_groups()
778 *ngroups = pctrl->community->functions[function].ngroups; in chv_get_function_groups()
785 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_pinmux_set_mux() local
790 grp = &pctrl->community->groups[group]; in chv_pinmux_set_mux()
792 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_pinmux_set_mux()
796 if (chv_pad_locked(pctrl, grp->pins[i])) { in chv_pinmux_set_mux()
797 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", in chv_pinmux_set_mux()
799 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_pinmux_set_mux()
822 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); in chv_pinmux_set_mux()
832 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); in chv_pinmux_set_mux()
838 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", in chv_pinmux_set_mux()
842 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_pinmux_set_mux()
851 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_gpio_request_enable() local
856 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_request_enable()
858 if (chv_pad_locked(pctrl, offset)) { in chv_gpio_request_enable()
859 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); in chv_gpio_request_enable()
862 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_request_enable()
869 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { in chv_gpio_request_enable()
870 if (pctrl->intr_lines[i] == offset) { in chv_gpio_request_enable()
871 pctrl->intr_lines[i] = 0; in chv_gpio_request_enable()
877 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); in chv_gpio_request_enable()
883 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); in chv_gpio_request_enable()
902 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_request_enable()
911 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_gpio_disable_free() local
916 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_disable_free()
918 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); in chv_gpio_disable_free()
922 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_disable_free()
929 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_gpio_set_direction() local
930 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); in chv_gpio_set_direction()
934 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_set_direction()
943 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_set_direction()
961 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_config_get() local
968 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_config_get()
969 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_config_get()
970 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); in chv_config_get()
971 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_config_get()
1038 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, in chv_config_set_pull() argument
1041 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); in chv_config_set_pull()
1045 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_config_set_pull()
1068 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_config_set_pull()
1086 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_config_set_pull()
1094 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_config_set_pull()
1099 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_config_set_pull()
1107 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in chv_config_set() local
1112 if (chv_pad_locked(pctrl, pin)) in chv_config_set()
1123 ret = chv_config_set_pull(pctrl, pin, param, arg); in chv_config_set()
1132 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, in chv_config_set()
1152 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, in chv_gpio_offset_to_pin() argument
1155 return pctrl->community->pins[offset].number; in chv_gpio_offset_to_pin()
1160 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); in chv_gpio_get() local
1161 int pin = chv_gpio_offset_to_pin(pctrl, offset); in chv_gpio_get()
1165 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_get()
1166 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_gpio_get()
1167 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_get()
1179 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); in chv_gpio_set() local
1180 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); in chv_gpio_set()
1185 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_set()
1187 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); in chv_gpio_set()
1197 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_set()
1202 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); in chv_gpio_get_direction() local
1203 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); in chv_gpio_get_direction()
1207 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_get_direction()
1208 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_gpio_get_direction()
1209 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_get_direction()
1243 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); in chv_gpio_irq_ack() local
1244 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); in chv_gpio_irq_ack()
1247 raw_spin_lock(&pctrl->lock); in chv_gpio_irq_ack()
1249 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_gpio_irq_ack()
1252 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); in chv_gpio_irq_ack()
1254 raw_spin_unlock(&pctrl->lock); in chv_gpio_irq_ack()
1260 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); in chv_gpio_irq_mask_unmask() local
1261 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); in chv_gpio_irq_mask_unmask()
1265 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_irq_mask_unmask()
1267 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_gpio_irq_mask_unmask()
1271 value = readl(pctrl->regs + CHV_INTMASK); in chv_gpio_irq_mask_unmask()
1276 chv_writel(value, pctrl->regs + CHV_INTMASK); in chv_gpio_irq_mask_unmask()
1278 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_irq_mask_unmask()
1305 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); in chv_gpio_irq_startup() local
1307 int pin = chv_gpio_offset_to_pin(pctrl, offset); in chv_gpio_irq_startup()
1312 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_irq_startup()
1313 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_gpio_irq_startup()
1317 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); in chv_gpio_irq_startup()
1323 if (!pctrl->intr_lines[intsel]) { in chv_gpio_irq_startup()
1325 pctrl->intr_lines[intsel] = offset; in chv_gpio_irq_startup()
1327 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_irq_startup()
1337 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); in chv_gpio_irq_type() local
1339 int pin = chv_gpio_offset_to_pin(pctrl, offset); in chv_gpio_irq_type()
1343 raw_spin_lock_irqsave(&pctrl->lock, flags); in chv_gpio_irq_type()
1358 if (!chv_pad_locked(pctrl, pin)) { in chv_gpio_irq_type()
1359 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); in chv_gpio_irq_type()
1381 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_gpio_irq_type()
1385 pctrl->intr_lines[value] = offset; in chv_gpio_irq_type()
1392 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in chv_gpio_irq_type()
1410 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); in chv_gpio_irq_handler() local
1417 pending = readl(pctrl->regs + CHV_INTSTAT); in chv_gpio_irq_handler()
1421 offset = pctrl->intr_lines[intr_line]; in chv_gpio_irq_handler()
1429 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) in chv_gpio_probe() argument
1432 struct gpio_chip *chip = &pctrl->chip; in chv_gpio_probe()
1437 chip->ngpio = pctrl->community->ngpios; in chv_gpio_probe()
1438 chip->label = dev_name(pctrl->dev); in chv_gpio_probe()
1439 chip->dev = pctrl->dev; in chv_gpio_probe()
1444 dev_err(pctrl->dev, "Failed to register gpiochip\n"); in chv_gpio_probe()
1448 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { in chv_gpio_probe()
1449 range = &pctrl->community->gpio_ranges[i]; in chv_gpio_probe()
1450 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, in chv_gpio_probe()
1453 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); in chv_gpio_probe()
1461 chv_writel(0, pctrl->regs + CHV_INTMASK); in chv_gpio_probe()
1462 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); in chv_gpio_probe()
1467 dev_err(pctrl->dev, "failed to add IRQ chip\n"); in chv_gpio_probe()
1483 struct chv_pinctrl *pctrl; in chv_pinctrl_probe() local
1492 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in chv_pinctrl_probe()
1493 if (!pctrl) in chv_pinctrl_probe()
1498 pctrl->community = chv_communities[i]; in chv_pinctrl_probe()
1504 raw_spin_lock_init(&pctrl->lock); in chv_pinctrl_probe()
1505 pctrl->dev = &pdev->dev; in chv_pinctrl_probe()
1508 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, in chv_pinctrl_probe()
1509 pctrl->community->npins, sizeof(*pctrl->saved_pin_context), in chv_pinctrl_probe()
1511 if (!pctrl->saved_pin_context) in chv_pinctrl_probe()
1516 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); in chv_pinctrl_probe()
1517 if (IS_ERR(pctrl->regs)) in chv_pinctrl_probe()
1518 return PTR_ERR(pctrl->regs); in chv_pinctrl_probe()
1526 pctrl->pctldesc = chv_pinctrl_desc; in chv_pinctrl_probe()
1527 pctrl->pctldesc.name = dev_name(&pdev->dev); in chv_pinctrl_probe()
1528 pctrl->pctldesc.pins = pctrl->community->pins; in chv_pinctrl_probe()
1529 pctrl->pctldesc.npins = pctrl->community->npins; in chv_pinctrl_probe()
1531 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); in chv_pinctrl_probe()
1532 if (IS_ERR(pctrl->pctldev)) { in chv_pinctrl_probe()
1534 return PTR_ERR(pctrl->pctldev); in chv_pinctrl_probe()
1537 ret = chv_gpio_probe(pctrl, irq); in chv_pinctrl_probe()
1539 pinctrl_unregister(pctrl->pctldev); in chv_pinctrl_probe()
1543 platform_set_drvdata(pdev, pctrl); in chv_pinctrl_probe()
1550 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); in chv_pinctrl_remove() local
1552 gpiochip_remove(&pctrl->chip); in chv_pinctrl_remove()
1553 pinctrl_unregister(pctrl->pctldev); in chv_pinctrl_remove()
1562 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); in chv_pinctrl_suspend() local
1565 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); in chv_pinctrl_suspend()
1567 for (i = 0; i < pctrl->community->npins; i++) { in chv_pinctrl_suspend()
1572 desc = &pctrl->community->pins[i]; in chv_pinctrl_suspend()
1573 if (chv_pad_locked(pctrl, desc->number)) in chv_pinctrl_suspend()
1576 ctx = &pctrl->saved_pin_context[i]; in chv_pinctrl_suspend()
1578 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); in chv_pinctrl_suspend()
1581 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); in chv_pinctrl_suspend()
1591 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); in chv_pinctrl_resume() local
1599 chv_writel(0, pctrl->regs + CHV_INTMASK); in chv_pinctrl_resume()
1601 for (i = 0; i < pctrl->community->npins; i++) { in chv_pinctrl_resume()
1607 desc = &pctrl->community->pins[i]; in chv_pinctrl_resume()
1608 if (chv_pad_locked(pctrl, desc->number)) in chv_pinctrl_resume()
1611 ctx = &pctrl->saved_pin_context[i]; in chv_pinctrl_resume()
1614 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); in chv_pinctrl_resume()
1618 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", in chv_pinctrl_resume()
1622 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); in chv_pinctrl_resume()
1626 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", in chv_pinctrl_resume()
1635 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); in chv_pinctrl_resume()
1636 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); in chv_pinctrl_resume()