Lines Matching refs:priv
225 struct scc_priv priv[2]; member
234 static void write_scc(struct scc_priv *priv, int reg, int val);
235 static void write_scc_data(struct scc_priv *priv, int val, int fast);
236 static int read_scc(struct scc_priv *priv, int reg);
237 static int read_scc_data(struct scc_priv *priv);
245 static inline void tx_on(struct scc_priv *priv);
246 static inline void rx_on(struct scc_priv *priv);
247 static inline void rx_off(struct scc_priv *priv);
248 static void start_timer(struct scc_priv *priv, int t, int r15);
253 static void rx_isr(struct scc_priv *priv);
254 static void special_condition(struct scc_priv *priv, int rc);
256 static void tx_isr(struct scc_priv *priv);
257 static void es_isr(struct scc_priv *priv);
258 static void tm_isr(struct scc_priv *priv);
293 if (info->priv[0].type == TYPE_TWIN) in dmascc_exit()
295 write_scc(&info->priv[0], R9, FHWRES); in dmascc_exit()
297 hw[info->priv[0].type].io_size); in dmascc_exit()
457 struct scc_priv *priv; in setup_adapter() local
486 priv = &info->priv[0]; in setup_adapter()
487 priv->type = type; in setup_adapter()
488 priv->card_base = card_base; in setup_adapter()
489 priv->scc_cmd = scc_base + SCCA_CMD; in setup_adapter()
490 priv->scc_data = scc_base + SCCA_DATA; in setup_adapter()
491 priv->register_lock = &info->register_lock; in setup_adapter()
494 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
497 write_scc(priv, R15, SHDLCE); in setup_adapter()
498 if (!read_scc(priv, R15)) { in setup_adapter()
503 write_scc_data(priv, 0, 0); in setup_adapter()
504 if (read_scc(priv, R0) & Tx_BUF_EMP) { in setup_adapter()
512 write_scc(priv, R15, 0); in setup_adapter()
525 write_scc(priv, R15, CTSIE); in setup_adapter()
526 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
527 write_scc(priv, R1, EXT_INT_ENAB); in setup_adapter()
543 write_scc(priv, R1, 0); in setup_adapter()
544 write_scc(priv, R15, 0); in setup_adapter()
545 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
558 priv = &info->priv[i]; in setup_adapter()
559 priv->type = type; in setup_adapter()
560 priv->chip = chip; in setup_adapter()
561 priv->dev = dev; in setup_adapter()
562 priv->info = info; in setup_adapter()
563 priv->channel = i; in setup_adapter()
564 spin_lock_init(&priv->ring_lock); in setup_adapter()
565 priv->register_lock = &info->register_lock; in setup_adapter()
566 priv->card_base = card_base; in setup_adapter()
567 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD); in setup_adapter()
568 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA); in setup_adapter()
569 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1); in setup_adapter()
570 priv->tmr_ctrl = tmr_base + TMR_CTRL; in setup_adapter()
571 priv->tmr_mode = i ? 0xb0 : 0x70; in setup_adapter()
572 priv->param.pclk_hz = hw[type].pclk_hz; in setup_adapter()
573 priv->param.brg_tc = -1; in setup_adapter()
574 priv->param.clocks = TCTRxCP | RCRTxCP; in setup_adapter()
575 priv->param.persist = 256; in setup_adapter()
576 priv->param.dma = -1; in setup_adapter()
577 INIT_WORK(&priv->rx_work, rx_bh); in setup_adapter()
578 dev->ml_priv = priv; in setup_adapter()
606 if (info->priv[0].type == TYPE_TWIN) in setup_adapter()
608 write_scc(&info->priv[0], R9, FHWRES); in setup_adapter()
621 static void write_scc(struct scc_priv *priv, int reg, int val) in write_scc() argument
624 switch (priv->type) { in write_scc()
627 outb(reg, priv->scc_cmd); in write_scc()
628 outb(val, priv->scc_cmd); in write_scc()
632 outb_p(reg, priv->scc_cmd); in write_scc()
633 outb_p(val, priv->scc_cmd); in write_scc()
636 spin_lock_irqsave(priv->register_lock, flags); in write_scc()
637 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc()
639 outb_p(reg, priv->scc_cmd); in write_scc()
640 outb_p(val, priv->scc_cmd); in write_scc()
641 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc()
642 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc()
648 static void write_scc_data(struct scc_priv *priv, int val, int fast) in write_scc_data() argument
651 switch (priv->type) { in write_scc_data()
653 outb(val, priv->scc_data); in write_scc_data()
656 outb_p(val, priv->scc_data); in write_scc_data()
660 outb_p(val, priv->scc_data); in write_scc_data()
662 spin_lock_irqsave(priv->register_lock, flags); in write_scc_data()
663 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc_data()
664 outb_p(val, priv->scc_data); in write_scc_data()
665 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc_data()
666 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc_data()
673 static int read_scc(struct scc_priv *priv, int reg) in read_scc() argument
677 switch (priv->type) { in read_scc()
680 outb(reg, priv->scc_cmd); in read_scc()
681 return inb(priv->scc_cmd); in read_scc()
684 outb_p(reg, priv->scc_cmd); in read_scc()
685 return inb_p(priv->scc_cmd); in read_scc()
687 spin_lock_irqsave(priv->register_lock, flags); in read_scc()
688 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc()
690 outb_p(reg, priv->scc_cmd); in read_scc()
691 rc = inb_p(priv->scc_cmd); in read_scc()
692 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc()
693 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc()
699 static int read_scc_data(struct scc_priv *priv) in read_scc_data() argument
703 switch (priv->type) { in read_scc_data()
705 return inb(priv->scc_data); in read_scc_data()
707 return inb_p(priv->scc_data); in read_scc_data()
709 spin_lock_irqsave(priv->register_lock, flags); in read_scc_data()
710 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc_data()
711 rc = inb_p(priv->scc_data); in read_scc_data()
712 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc_data()
713 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc_data()
721 struct scc_priv *priv = dev->ml_priv; in scc_open() local
722 struct scc_info *info = priv->info; in scc_open()
723 int card_base = priv->card_base; in scc_open()
734 if (priv->param.dma >= 0) { in scc_open()
735 if (request_dma(priv->param.dma, "dmascc")) { in scc_open()
741 clear_dma_ff(priv->param.dma); in scc_open()
747 priv->rx_ptr = 0; in scc_open()
748 priv->rx_over = 0; in scc_open()
749 priv->rx_head = priv->rx_tail = priv->rx_count = 0; in scc_open()
750 priv->state = IDLE; in scc_open()
751 priv->tx_head = priv->tx_tail = priv->tx_count = 0; in scc_open()
752 priv->tx_ptr = 0; in scc_open()
755 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
757 write_scc(priv, R4, SDLC | X1CLK); in scc_open()
759 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in scc_open()
761 write_scc(priv, R3, Rx8); in scc_open()
763 write_scc(priv, R5, Tx8); in scc_open()
765 write_scc(priv, R6, 0); in scc_open()
767 write_scc(priv, R7, FLAG); in scc_open()
768 switch (priv->chip) { in scc_open()
771 write_scc(priv, R15, SHDLCE); in scc_open()
773 write_scc(priv, R7, AUTOEOM); in scc_open()
774 write_scc(priv, R15, 0); in scc_open()
778 write_scc(priv, R15, SHDLCE); in scc_open()
798 if (priv->param.dma >= 0) { in scc_open()
799 if (priv->type == TYPE_TWIN) in scc_open()
800 write_scc(priv, R7, AUTOEOM | TXFIFOE); in scc_open()
802 write_scc(priv, R7, AUTOEOM); in scc_open()
804 write_scc(priv, R7, AUTOEOM | RXFIFOH); in scc_open()
806 write_scc(priv, R15, 0); in scc_open()
810 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ)); in scc_open()
813 if (priv->param.brg_tc >= 0) { in scc_open()
815 write_scc(priv, R12, priv->param.brg_tc & 0xFF); in scc_open()
816 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF); in scc_open()
819 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL); in scc_open()
821 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL); in scc_open()
824 write_scc(priv, R14, DTRREQ | BRSRC); in scc_open()
828 if (priv->type == TYPE_TWIN) { in scc_open()
831 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
834 write_scc(priv, R11, priv->param.clocks); in scc_open()
835 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) { in scc_open()
838 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
843 if (priv->type == TYPE_TWIN) { in scc_open()
846 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)), in scc_open()
851 priv->rr0 = read_scc(priv, R0); in scc_open()
853 write_scc(priv, R15, DCDIE); in scc_open()
863 struct scc_priv *priv = dev->ml_priv; in scc_close() local
864 struct scc_info *info = priv->info; in scc_close()
865 int card_base = priv->card_base; in scc_close()
869 if (priv->type == TYPE_TWIN) { in scc_close()
872 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)), in scc_close()
877 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
878 if (priv->param.dma >= 0) { in scc_close()
879 if (priv->type == TYPE_TWIN) in scc_close()
881 free_dma(priv->param.dma); in scc_close()
892 struct scc_priv *priv = dev->ml_priv; in scc_ioctl() local
897 (ifr->ifr_data, &priv->param, in scc_ioctl()
907 (&priv->param, ifr->ifr_data, in scc_ioctl()
919 struct scc_priv *priv = dev->ml_priv; in scc_send_packet() local
930 i = priv->tx_head; in scc_send_packet()
931 skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1); in scc_send_packet()
932 priv->tx_len[i] = skb->len - 1; in scc_send_packet()
936 spin_lock_irqsave(&priv->ring_lock, flags); in scc_send_packet()
938 priv->tx_head = (i + 1) % NUM_TX_BUF; in scc_send_packet()
939 priv->tx_count++; in scc_send_packet()
944 if (priv->tx_count < NUM_TX_BUF) in scc_send_packet()
948 if (priv->state == IDLE) { in scc_send_packet()
950 priv->state = TX_HEAD; in scc_send_packet()
951 priv->tx_start = jiffies; in scc_send_packet()
952 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); in scc_send_packet()
953 write_scc(priv, R15, 0); in scc_send_packet()
954 start_timer(priv, priv->param.txdelay, 0); in scc_send_packet()
958 spin_unlock_irqrestore(&priv->ring_lock, flags); in scc_send_packet()
973 static inline void tx_on(struct scc_priv *priv) in tx_on() argument
978 if (priv->param.dma >= 0) { in tx_on()
979 n = (priv->chip == Z85230) ? 3 : 1; in tx_on()
982 set_dma_mode(priv->param.dma, DMA_MODE_WRITE); in tx_on()
983 set_dma_addr(priv->param.dma, in tx_on()
984 (int) priv->tx_buf[priv->tx_tail] + n); in tx_on()
985 set_dma_count(priv->param.dma, in tx_on()
986 priv->tx_len[priv->tx_tail] - n); in tx_on()
989 write_scc(priv, R15, TxUIE); in tx_on()
991 if (priv->type == TYPE_TWIN) in tx_on()
992 outb((priv->param.dma == in tx_on()
994 priv->card_base + TWIN_DMA_CFG); in tx_on()
996 write_scc(priv, R1, in tx_on()
1000 spin_lock_irqsave(priv->register_lock, flags); in tx_on()
1002 write_scc_data(priv, in tx_on()
1003 priv->tx_buf[priv->tx_tail][i], 1); in tx_on()
1004 enable_dma(priv->param.dma); in tx_on()
1005 spin_unlock_irqrestore(priv->register_lock, flags); in tx_on()
1007 write_scc(priv, R15, TxUIE); in tx_on()
1008 write_scc(priv, R1, in tx_on()
1010 tx_isr(priv); in tx_on()
1013 if (priv->chip == Z8530) in tx_on()
1014 write_scc(priv, R0, RES_EOM_L); in tx_on()
1018 static inline void rx_on(struct scc_priv *priv) in rx_on() argument
1023 while (read_scc(priv, R0) & Rx_CH_AV) in rx_on()
1024 read_scc_data(priv); in rx_on()
1025 priv->rx_over = 0; in rx_on()
1026 if (priv->param.dma >= 0) { in rx_on()
1029 set_dma_mode(priv->param.dma, DMA_MODE_READ); in rx_on()
1030 set_dma_addr(priv->param.dma, in rx_on()
1031 (int) priv->rx_buf[priv->rx_head]); in rx_on()
1032 set_dma_count(priv->param.dma, BUF_SIZE); in rx_on()
1034 enable_dma(priv->param.dma); in rx_on()
1036 if (priv->type == TYPE_TWIN) { in rx_on()
1037 outb((priv->param.dma == in rx_on()
1039 priv->card_base + TWIN_DMA_CFG); in rx_on()
1042 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | in rx_on()
1046 priv->rx_ptr = 0; in rx_on()
1048 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | in rx_on()
1051 write_scc(priv, R0, ERR_RES); in rx_on()
1052 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB); in rx_on()
1056 static inline void rx_off(struct scc_priv *priv) in rx_off() argument
1059 write_scc(priv, R3, Rx8); in rx_off()
1061 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in rx_off()
1062 outb(0, priv->card_base + TWIN_DMA_CFG); in rx_off()
1064 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in rx_off()
1066 if (priv->param.dma >= 0) in rx_off()
1067 disable_dma(priv->param.dma); in rx_off()
1071 static void start_timer(struct scc_priv *priv, int t, int r15) in start_timer() argument
1073 outb(priv->tmr_mode, priv->tmr_ctrl); in start_timer()
1075 tm_isr(priv); in start_timer()
1077 outb(t & 0xFF, priv->tmr_cnt); in start_timer()
1078 outb((t >> 8) & 0xFF, priv->tmr_cnt); in start_timer()
1079 if (priv->type != TYPE_TWIN) { in start_timer()
1080 write_scc(priv, R15, r15 | CTSIE); in start_timer()
1081 priv->rr0 |= CTS; in start_timer()
1098 while ((is = read_scc(&info->priv[0], R3)) && i--) { in z8530_isr()
1100 rx_isr(&info->priv[0]); in z8530_isr()
1102 tx_isr(&info->priv[0]); in z8530_isr()
1104 es_isr(&info->priv[0]); in z8530_isr()
1106 rx_isr(&info->priv[1]); in z8530_isr()
1108 tx_isr(&info->priv[1]); in z8530_isr()
1110 es_isr(&info->priv[1]); in z8530_isr()
1112 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1128 spin_lock(info->priv[0].register_lock); in scc_isr()
1141 if (info->priv[0].type == TYPE_TWIN) { in scc_isr()
1142 int is, card_base = info->priv[0].card_base; in scc_isr()
1149 tm_isr(&info->priv[0]); in scc_isr()
1152 tm_isr(&info->priv[1]); in scc_isr()
1157 spin_unlock(info->priv[0].register_lock); in scc_isr()
1162 static void rx_isr(struct scc_priv *priv) in rx_isr() argument
1164 if (priv->param.dma >= 0) { in rx_isr()
1166 special_condition(priv, read_scc(priv, R1)); in rx_isr()
1167 write_scc(priv, R0, ERR_RES); in rx_isr()
1172 while (read_scc(priv, R0) & Rx_CH_AV) { in rx_isr()
1173 rc = read_scc(priv, R1); in rx_isr()
1174 if (priv->rx_ptr < BUF_SIZE) in rx_isr()
1175 priv->rx_buf[priv->rx_head][priv-> in rx_isr()
1177 read_scc_data(priv); in rx_isr()
1179 priv->rx_over = 2; in rx_isr()
1180 read_scc_data(priv); in rx_isr()
1182 special_condition(priv, rc); in rx_isr()
1188 static void special_condition(struct scc_priv *priv, int rc) in special_condition() argument
1197 priv->rx_over = 1; in special_condition()
1198 if (priv->param.dma < 0) in special_condition()
1199 write_scc(priv, R0, ERR_RES); in special_condition()
1202 if (priv->param.dma >= 0) { in special_condition()
1204 cb = BUF_SIZE - get_dma_residue(priv->param.dma) - in special_condition()
1208 cb = priv->rx_ptr - 2; in special_condition()
1210 if (priv->rx_over) { in special_condition()
1212 priv->dev->stats.rx_errors++; in special_condition()
1213 if (priv->rx_over == 2) in special_condition()
1214 priv->dev->stats.rx_length_errors++; in special_condition()
1216 priv->dev->stats.rx_fifo_errors++; in special_condition()
1217 priv->rx_over = 0; in special_condition()
1221 priv->dev->stats.rx_errors++; in special_condition()
1222 priv->dev->stats.rx_crc_errors++; in special_condition()
1226 if (priv->rx_count < NUM_RX_BUF - 1) { in special_condition()
1228 priv->rx_len[priv->rx_head] = cb; in special_condition()
1229 priv->rx_head = in special_condition()
1230 (priv->rx_head + in special_condition()
1232 priv->rx_count++; in special_condition()
1233 schedule_work(&priv->rx_work); in special_condition()
1235 priv->dev->stats.rx_errors++; in special_condition()
1236 priv->dev->stats.rx_over_errors++; in special_condition()
1241 if (priv->param.dma >= 0) { in special_condition()
1243 set_dma_addr(priv->param.dma, in special_condition()
1244 (int) priv->rx_buf[priv->rx_head]); in special_condition()
1245 set_dma_count(priv->param.dma, BUF_SIZE); in special_condition()
1248 priv->rx_ptr = 0; in special_condition()
1256 struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work); in rx_bh() local
1257 int i = priv->rx_tail; in rx_bh()
1263 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1264 while (priv->rx_count) { in rx_bh()
1265 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1266 cb = priv->rx_len[i]; in rx_bh()
1271 priv->dev->stats.rx_dropped++; in rx_bh()
1276 memcpy(&data[1], priv->rx_buf[i], cb); in rx_bh()
1277 skb->protocol = ax25_type_trans(skb, priv->dev); in rx_bh()
1279 priv->dev->stats.rx_packets++; in rx_bh()
1280 priv->dev->stats.rx_bytes += cb; in rx_bh()
1282 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1284 priv->rx_tail = i = (i + 1) % NUM_RX_BUF; in rx_bh()
1285 priv->rx_count--; in rx_bh()
1287 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1291 static void tx_isr(struct scc_priv *priv) in tx_isr() argument
1293 int i = priv->tx_tail, p = priv->tx_ptr; in tx_isr()
1297 if (p == priv->tx_len[i]) { in tx_isr()
1298 write_scc(priv, R0, RES_Tx_P); in tx_isr()
1303 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) { in tx_isr()
1304 write_scc_data(priv, priv->tx_buf[i][p++], 0); in tx_isr()
1308 if (!priv->tx_ptr && p && priv->chip == Z8530) in tx_isr()
1309 write_scc(priv, R0, RES_EOM_L); in tx_isr()
1311 priv->tx_ptr = p; in tx_isr()
1315 static void es_isr(struct scc_priv *priv) in es_isr() argument
1321 rr0 = read_scc(priv, R0); in es_isr()
1322 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1323 drr0 = priv->rr0 ^ rr0; in es_isr()
1324 priv->rr0 = rr0; in es_isr()
1328 if (priv->state == TX_DATA) { in es_isr()
1330 i = priv->tx_tail; in es_isr()
1331 if (priv->param.dma >= 0) { in es_isr()
1332 disable_dma(priv->param.dma); in es_isr()
1334 res = get_dma_residue(priv->param.dma); in es_isr()
1337 res = priv->tx_len[i] - priv->tx_ptr; in es_isr()
1338 priv->tx_ptr = 0; in es_isr()
1341 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in es_isr()
1342 outb(0, priv->card_base + TWIN_DMA_CFG); in es_isr()
1344 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in es_isr()
1347 priv->dev->stats.tx_errors++; in es_isr()
1348 priv->dev->stats.tx_fifo_errors++; in es_isr()
1350 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1351 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1354 priv->dev->stats.tx_packets++; in es_isr()
1355 priv->dev->stats.tx_bytes += priv->tx_len[i]; in es_isr()
1357 priv->tx_tail = (i + 1) % NUM_TX_BUF; in es_isr()
1358 priv->tx_count--; in es_isr()
1360 netif_wake_queue(priv->dev); in es_isr()
1363 write_scc(priv, R15, 0); in es_isr()
1364 if (priv->tx_count && in es_isr()
1365 (jiffies - priv->tx_start) < priv->param.txtimeout) { in es_isr()
1366 priv->state = TX_PAUSE; in es_isr()
1367 start_timer(priv, priv->param.txpause, 0); in es_isr()
1369 priv->state = TX_TAIL; in es_isr()
1370 start_timer(priv, priv->param.txtail, 0); in es_isr()
1377 switch (priv->state) { in es_isr()
1380 priv->state = DCD_ON; in es_isr()
1381 write_scc(priv, R15, 0); in es_isr()
1382 start_timer(priv, priv->param.dcdon, 0); in es_isr()
1385 switch (priv->state) { in es_isr()
1387 rx_off(priv); in es_isr()
1388 priv->state = DCD_OFF; in es_isr()
1389 write_scc(priv, R15, 0); in es_isr()
1390 start_timer(priv, priv->param.dcdoff, 0); in es_isr()
1396 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN) in es_isr()
1397 tm_isr(priv); in es_isr()
1402 static void tm_isr(struct scc_priv *priv) in tm_isr() argument
1404 switch (priv->state) { in tm_isr()
1407 tx_on(priv); in tm_isr()
1408 priv->state = TX_DATA; in tm_isr()
1411 write_scc(priv, R5, TxCRC_ENAB | Tx8); in tm_isr()
1412 priv->state = RTS_OFF; in tm_isr()
1413 if (priv->type != TYPE_TWIN) in tm_isr()
1414 write_scc(priv, R15, 0); in tm_isr()
1415 start_timer(priv, priv->param.rtsoff, 0); in tm_isr()
1418 write_scc(priv, R15, DCDIE); in tm_isr()
1419 priv->rr0 = read_scc(priv, R0); in tm_isr()
1420 if (priv->rr0 & DCD) { in tm_isr()
1421 priv->dev->stats.collisions++; in tm_isr()
1422 rx_on(priv); in tm_isr()
1423 priv->state = RX_ON; in tm_isr()
1425 priv->state = WAIT; in tm_isr()
1426 start_timer(priv, priv->param.waittime, DCDIE); in tm_isr()
1430 if (priv->tx_count) { in tm_isr()
1431 priv->state = TX_HEAD; in tm_isr()
1432 priv->tx_start = jiffies; in tm_isr()
1433 write_scc(priv, R5, in tm_isr()
1435 write_scc(priv, R15, 0); in tm_isr()
1436 start_timer(priv, priv->param.txdelay, 0); in tm_isr()
1438 priv->state = IDLE; in tm_isr()
1439 if (priv->type != TYPE_TWIN) in tm_isr()
1440 write_scc(priv, R15, DCDIE); in tm_isr()
1445 write_scc(priv, R15, DCDIE); in tm_isr()
1446 priv->rr0 = read_scc(priv, R0); in tm_isr()
1447 if (priv->rr0 & DCD) { in tm_isr()
1448 rx_on(priv); in tm_isr()
1449 priv->state = RX_ON; in tm_isr()
1451 priv->state = WAIT; in tm_isr()
1452 start_timer(priv, in tm_isr()
1453 random() / priv->param.persist * in tm_isr()
1454 priv->param.slottime, DCDIE); in tm_isr()