294 			outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);  in dmascc_exit()
372 				outb(0x36, tcmd[i]);  in dmascc_init()
373 				outb((hw[h].tmr_hz / TMR_0_HZ) & 0xFF,  in dmascc_init()
375 				outb((hw[h].tmr_hz / TMR_0_HZ) >> 8,  in dmascc_init()
378 				outb(0x70, tcmd[i]);  in dmascc_init()
379 				outb((TMR_0_HZ / HZ * 10) & 0xFF, t1[i]);  in dmascc_init()
380 				outb((TMR_0_HZ / HZ * 10) >> 8, t1[i]);  in dmascc_init()
385 				outb(0xb0, tcmd[i]);  in dmascc_init()
396 					outb(0x40, tcmd[i]);  in dmascc_init()
519 		outb(0, card_base + TWIN_DMA_CFG);  in setup_adapter()
523 		outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);  in setup_adapter()
531 	outb(1, tmr_base + TMR_CNT1);  in setup_adapter()
532 	outb(0, tmr_base + TMR_CNT1);  in setup_adapter()
607 		outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);  in setup_adapter()
627 			outb(reg, priv->scc_cmd);  in write_scc()
628 		outb(val, priv->scc_cmd);  in write_scc()
641 		outb(1, priv->card_base + PI_DREQ_MASK);  in write_scc()
653 		outb(val, priv->scc_data);  in write_scc_data()
665 			outb(1, priv->card_base + PI_DREQ_MASK);  in write_scc_data()
680 			outb(reg, priv->scc_cmd);  in read_scc()
692 		outb(1, priv->card_base + PI_DREQ_MASK);  in read_scc()
712 		outb(1, priv->card_base + PI_DREQ_MASK);  in read_scc_data()
830 		outb((info->twin_serial_cfg &=  in scc_open()
837 		outb((info->twin_serial_cfg |=  in scc_open()
845 		outb((info->twin_serial_cfg |= TWIN_EI |  in scc_open()
871 		outb((info->twin_serial_cfg &=  in scc_close()
880 			outb(0, card_base + TWIN_DMA_CFG);  in scc_close()
992 			outb((priv->param.dma ==  in tx_on()
1037 			outb((priv->param.dma ==  in rx_on()
1062 		outb(0, priv->card_base + TWIN_DMA_CFG);  in rx_off()
1073 	outb(priv->tmr_mode, priv->tmr_ctrl);  in start_timer()
1077 		outb(t & 0xFF, priv->tmr_cnt);  in start_timer()
1078 		outb((t >> 8) & 0xFF, priv->tmr_cnt);  in start_timer()
1342 			outb(0, priv->card_base + TWIN_DMA_CFG);  in es_isr()