Lines Matching refs:mvreg_write
546 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) in mvreg_write() function
647 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
653 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
679 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
699 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
723 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_max_rx_size_set()
739 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_offset_set()
756 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_pend_desc_add()
792 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); in mvneta_rxq_buf_size_set()
803 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_bm_disable()
819 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); in mvneta_port_up()
822 mvreg_write(pp, MVNETA_RXQ_CMD, BIT(rxq_def)); in mvneta_port_up()
836 mvreg_write(pp, MVNETA_RXQ_CMD, in mvneta_port_down()
859 mvreg_write(pp, MVNETA_TXQ_CMD, in mvneta_port_down()
904 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_enable()
915 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_disable()
936 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); in mvneta_set_ucast_table()
953 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); in mvneta_set_special_mcast_table()
973 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); in mvneta_set_other_mcast_table()
992 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); in mvneta_defaults_set()
993 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); in mvneta_defaults_set()
994 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_defaults_set()
997 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_defaults_set()
998 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_defaults_set()
999 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_defaults_set()
1000 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); in mvneta_defaults_set()
1003 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); in mvneta_defaults_set()
1009 mvreg_write(pp, MVNETA_CPU_MAP(cpu), in mvneta_defaults_set()
1014 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); in mvneta_defaults_set()
1015 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); in mvneta_defaults_set()
1018 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); in mvneta_defaults_set()
1020 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); in mvneta_defaults_set()
1021 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); in mvneta_defaults_set()
1024 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); in mvneta_defaults_set()
1025 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); in mvneta_defaults_set()
1029 mvreg_write(pp, MVNETA_ACC_MODE, val); in mvneta_defaults_set()
1033 mvreg_write(pp, MVNETA_PORT_CONFIG, val); in mvneta_defaults_set()
1036 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); in mvneta_defaults_set()
1037 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); in mvneta_defaults_set()
1052 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); in mvneta_defaults_set()
1059 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); in mvneta_defaults_set()
1069 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_defaults_set()
1072 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); in mvneta_defaults_set()
1078 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_defaults_set()
1086 mvreg_write(pp, MVNETA_INTR_ENABLE, in mvneta_defaults_set()
1108 mvreg_write(pp, MVNETA_TX_MTU, val); in mvneta_txq_max_tx_size_set()
1118 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); in mvneta_txq_max_tx_size_set()
1128 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); in mvneta_txq_max_tx_size_set()
1160 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); in mvneta_set_ucast_addr()
1175 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); in mvneta_mac_addr_set()
1176 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); in mvneta_mac_addr_set()
1189 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), in mvneta_rx_pkts_coal_set()
1206 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); in mvneta_rx_time_coal_set()
1221 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); in mvneta_tx_done_pkts_coal_set()
1244 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
1249 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
1971 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, in mvneta_set_special_mcast_addr()
2004 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); in mvneta_set_other_mcast_addr()
2064 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); in mvneta_rx_unicast_promisc_set()
2065 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); in mvneta_rx_unicast_promisc_set()
2072 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); in mvneta_rx_unicast_promisc_set()
2073 mvreg_write(pp, MVNETA_TYPE_PRIO, val); in mvneta_rx_unicast_promisc_set()
2170 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_poll()
2234 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); in mvneta_tx_reset()
2235 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); in mvneta_tx_reset()
2240 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); in mvneta_rx_reset()
2241 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); in mvneta_rx_reset()
2266 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); in mvneta_rxq_init()
2267 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); in mvneta_rxq_init()
2330 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); in mvneta_txq_init()
2331 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); in mvneta_txq_init()
2334 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); in mvneta_txq_init()
2335 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); in mvneta_txq_init()
2382 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); in mvneta_txq_deinit()
2383 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); in mvneta_txq_deinit()
2386 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); in mvneta_txq_deinit()
2387 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); in mvneta_txq_deinit()
2456 mvreg_write(pp, MVNETA_INTR_NEW_MASK, in mvneta_start_dev()
2460 mvreg_write(pp, MVNETA_INTR_MISC_MASK, in mvneta_start_dev()
2490 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_stop_dev()
2491 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); in mvneta_stop_dev()
2494 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_stop_dev()
2495 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_stop_dev()
2496 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_stop_dev()
2648 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_adjust_link()
2672 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, in mvneta_adjust_link()
2682 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, in mvneta_adjust_link()
2780 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_percpu_notifier()
2781 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_percpu_notifier()
2782 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_percpu_notifier()
2791 mvreg_write(pp, MVNETA_INTR_NEW_MASK, in mvneta_percpu_notifier()
2795 mvreg_write(pp, MVNETA_INTR_MISC_MASK, in mvneta_percpu_notifier()
2805 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_percpu_notifier()
2806 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_percpu_notifier()
2807 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_percpu_notifier()
2823 mvreg_write(pp, MVNETA_INTR_NEW_MASK, in mvneta_percpu_notifier()
2827 mvreg_write(pp, MVNETA_INTR_MISC_MASK, in mvneta_percpu_notifier()
3177 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); in mvneta_conf_mbus_windows()
3178 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); in mvneta_conf_mbus_windows()
3181 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); in mvneta_conf_mbus_windows()
3189 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | in mvneta_conf_mbus_windows()
3192 mvreg_write(pp, MVNETA_WIN_SIZE(i), in mvneta_conf_mbus_windows()
3199 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); in mvneta_conf_mbus_windows()
3200 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); in mvneta_conf_mbus_windows()
3209 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); in mvneta_port_power_up()
3218 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); in mvneta_port_power_up()
3222 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); in mvneta_port_power_up()
3238 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); in mvneta_port_power_up()