552 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)  in mvreg_read()  function
582 		dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));  in mvneta_mib_counters_clear()
583 	dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);  in mvneta_mib_counters_clear()
584 	dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);  in mvneta_mib_counters_clear()
663 	val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));  in mvneta_rxq_busy_desc_num_get()
719 	val =  mvreg_read(pp, MVNETA_GMAC_CTRL_0);  in mvneta_max_rx_size_set()
734 	val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));  in mvneta_rxq_offset_set()
787 	val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));  in mvneta_rxq_buf_size_set()
801 	val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));  in mvneta_rxq_bm_disable()
832 	val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;  in mvneta_port_down()
850 		val = mvreg_read(pp, MVNETA_RXQ_CMD);  in mvneta_port_down()
856 	val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;  in mvneta_port_down()
874 		val = mvreg_read(pp, MVNETA_TXQ_CMD);  in mvneta_port_down()
889 		val = mvreg_read(pp, MVNETA_PORT_STATUS);  in mvneta_port_down()
902 	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);  in mvneta_port_enable()
913 	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);  in mvneta_port_disable()
1057 	val = mvreg_read(pp, MVNETA_UNIT_CONTROL);  in mvneta_defaults_set()
1062 		val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);  in mvneta_defaults_set()
1070 		val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);  in mvneta_defaults_set()
1074 		val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);  in mvneta_defaults_set()
1105 	val = mvreg_read(pp, MVNETA_TX_MTU);  in mvneta_txq_max_tx_size_set()
1111 	val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);  in mvneta_txq_max_tx_size_set()
1121 		val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));  in mvneta_txq_max_tx_size_set()
1150 	unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));  in mvneta_set_ucast_addr()
1216 	val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));  in mvneta_tx_done_pkts_coal_set()
1259 	val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));  in mvneta_txq_sent_desc_num_get()
1961 	smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST  in mvneta_set_special_mcast_addr()
1994 	omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);  in mvneta_set_other_mcast_addr()
2055 	port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);  in mvneta_rx_unicast_promisc_set()
2057 	val = mvreg_read(pp, MVNETA_TYPE_PRIO);  in mvneta_rx_unicast_promisc_set()
2129 	u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);  in mvneta_fixed_link_update()
2166 	cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);  in mvneta_poll()
2168 		u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);  in mvneta_poll()
2594 	mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);  in mvneta_get_mac_addr()
2595 	mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);  in mvneta_get_mac_addr()
2635 			val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);  in mvneta_adjust_link()
2668 				u32 val = mvreg_read(pp,  in mvneta_adjust_link()
2678 				u32 val = mvreg_read(pp,  in mvneta_adjust_link()
3211 	ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);  in mvneta_port_power_up()
3240 	while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &  in mvneta_port_power_up()