Lines Matching refs:params
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_hw_pci_read_cfg4()
161 if (is_t4(adap->params.chip)) in t4_hw_pci_read_cfg4()
354 if (is_t4(adap->params.chip)) { in t4_edc_err_read()
455 if (is_t4(adap->params.chip)) in t4_memory_rw()
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); in t4_memory_rw()
619 if (is_t4(adap->params.chip)) { in t4_get_window()
672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in t4_get_regs_len()
2507 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
2829 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) in t4_read_flash()
2867 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) in t4_write_flash()
2986 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_check_fw_version()
2988 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
2991 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
2996 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers); in t4_check_fw_version()
2997 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers); in t4_check_fw_version()
2998 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers); in t4_check_fw_version()
3162 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
3163 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in t4_prep_fw()
3181 if (end >= adapter->params.sf_nsec) in t4_flash_erase_sectors()
3209 if (adapter->params.sf_size == 0x100000) in t4_flash_cfg_addr()
3226 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
3227 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || in t4_fw_matches_chip()
3228 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) in t4_fw_matches_chip()
3233 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); in t4_fw_matches_chip()
3253 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
3254 unsigned int fw_img_start = adap->params.sf_fw_start; in t4_load_fw()
3321 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_load_fw()
3340 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_phy_fw_ver()
3411 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3441 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3785 if (is_t4(adapter->params.chip)) in pcie_intr_handler()
3867 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in sge_intr_handler()
4055 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); in le_intr_handler()
4166 if (is_t4(adapter->params.chip)) { in mem_intr_handler()
4213 if (is_t5(adap->params.chip)) in ma_intr_handler()
4270 if (is_t4(adap->params.chip)) in xgmac_intr_handler()
4347 if (is_t5(adapter->params.chip) && (cause & MC1_F)) in t4_slow_intr_handler()
4395 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_enable()
4398 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in t4_intr_enable()
4422 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_disable()
4671 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && in t4_write_rss_key()
4727 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) { in t4_read_rss_vf_config()
4839 int nchan = adap->params.arch.nchan; in t4_tp_get_err_stats()
4871 int nchan = adap->params.arch.nchan; in t4_tp_get_cpl_stats()
5096 u64 v = bytes256 * adap->params.vpd.cclk; in chan_rate()
5117 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5125 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5172 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 || in t4_set_trace_filter()
5193 (is_t4(adap->params.chip) ? in t4_set_trace_filter()
5220 if (is_t4(adap->params.chip)) { in t4_get_trace_filter()
5260 if (is_t4(adap->params.chip)) { in t4_pmtx_get_stats()
5287 if (is_t4(adap->params.chip)) { in t4_pmrx_get_stats()
5384 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
5467 (is_t4(adap->params.chip) ? \ in t4_get_lb_stats()
5701 if (is_t4(adapter->params.chip)) { in t4_sge_decode_idma_state()
6128 if (is_t4(adap->params.chip)) { in t4_fixup_host_params()
6240 unsigned int vf, unsigned int nparams, const u32 *params, in t4_query_params_rw() argument
6258 *p++ = cpu_to_be32(*params++); in t4_query_params_rw()
6272 unsigned int vf, unsigned int nparams, const u32 *params, in t4_query_params() argument
6275 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); in t4_query_params()
6294 unsigned int nparams, const u32 *params, in t4_set_params_timeout() argument
6311 *p++ = cpu_to_be32(*params++); in t4_set_params_timeout()
6332 unsigned int vf, unsigned int nparams, const u32 *params, in t4_set_params() argument
6335 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, in t4_set_params()
6543 unsigned int max_naddr = adap->params.arch.mps_tcam_size; in t4_alloc_mac_filt()
6633 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; in t4_change_mac()
6985 adap->params.sf_size = supported_flash[ret].size_mb; in get_flash_params()
6986 adap->params.sf_nsec = in get_flash_params()
6987 adap->params.sf_size / SF_SEC_SIZE; in get_flash_params()
6995 adap->params.sf_nsec = 1 << (info - 16); in get_flash_params()
6997 adap->params.sf_nsec = 64; in get_flash_params()
7000 adap->params.sf_size = 1 << info; in get_flash_params()
7001 adap->params.sf_fw_start = in get_flash_params()
7004 if (adap->params.sf_size < FLASH_MIN_SIZE) in get_flash_params()
7006 adap->params.sf_size, FLASH_MIN_SIZE); in get_flash_params()
7041 get_pci_mode(adapter, &adapter->params.pci); in t4_prep_adapter()
7054 adapter->params.chip = 0; in t4_prep_adapter()
7057 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); in t4_prep_adapter()
7058 adapter->params.arch.sge_fl_db = DBPRIO_F; in t4_prep_adapter()
7059 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
7061 adapter->params.arch.mps_rplc_size = 128; in t4_prep_adapter()
7062 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
7063 adapter->params.arch.vfcount = 128; in t4_prep_adapter()
7066 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); in t4_prep_adapter()
7067 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F; in t4_prep_adapter()
7068 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
7070 adapter->params.arch.mps_rplc_size = 128; in t4_prep_adapter()
7071 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
7072 adapter->params.arch.vfcount = 128; in t4_prep_adapter()
7075 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); in t4_prep_adapter()
7076 adapter->params.arch.sge_fl_db = 0; in t4_prep_adapter()
7077 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
7079 adapter->params.arch.mps_rplc_size = 256; in t4_prep_adapter()
7080 adapter->params.arch.nchan = 2; in t4_prep_adapter()
7081 adapter->params.arch.vfcount = 256; in t4_prep_adapter()
7089 adapter->params.cim_la_size = CIMLA_SIZE; in t4_prep_adapter()
7090 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t4_prep_adapter()
7095 adapter->params.nports = 1; in t4_prep_adapter()
7096 adapter->params.portvec = 1; in t4_prep_adapter()
7097 adapter->params.vpd.cclk = 50000; in t4_prep_adapter()
7142 if (!user && is_t4(adapter->params.chip)) in t4_bar2_sge_qregs()
7147 page_shift = adapter->params.sge.hps + 10; in t4_bar2_sge_qregs()
7153 ? adapter->params.sge.eq_qpp in t4_bar2_sge_qregs()
7154 : adapter->params.sge.iq_qpp); in t4_bar2_sge_qregs()
7203 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
7256 struct sge_params *sge_params = &adapter->params.sge; in t4_init_sge_params()
7291 adap->params.tp.tre = TIMERRESOLUTION_G(v); in t4_init_tp_params()
7292 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); in t4_init_tp_params()
7296 adap->params.tp.tx_modq[chan] = chan; in t4_init_tp_params()
7302 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
7304 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
7308 &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
7311 &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
7319 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); in t4_init_tp_params()
7320 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); in t4_init_tp_params()
7321 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); in t4_init_tp_params()
7322 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
7328 if ((adap->params.tp.ingress_config & VNIC_F) == 0) in t4_init_tp_params()
7329 adap->params.tp.vnic_shift = -1; in t4_init_tp_params()
7345 unsigned int filter_mode = adap->params.tp.vlan_pri_map; in t4_filter_field_shift()
7426 while ((adap->params.portvec & (1 << j)) == 0) in t4_port_init()
7485 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cimq_cfg()
7564 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cim_obq()
7684 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
7729 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); in t4_tp_read_la()
7741 val |= adap->params.tp.la_mask; in t4_tp_read_la()
7755 cfg | adap->params.tp.la_mask); in t4_tp_read_la()