Lines Matching refs:adap
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, in t4_read_indirect() argument
118 t4_write_reg(adap, addr_reg, start_idx); in t4_read_indirect()
119 *vals++ = t4_read_reg(adap, data_reg); in t4_read_indirect()
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, in t4_write_indirect() argument
141 t4_write_reg(adap, addr_reg, start_idx++); in t4_write_indirect()
142 t4_write_reg(adap, data_reg, *vals++); in t4_write_indirect()
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) in t4_hw_pci_read_cfg4() argument
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); in t4_hw_pci_read_cfg4()
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_hw_pci_read_cfg4()
161 if (is_t4(adap->params.chip)) in t4_hw_pci_read_cfg4()
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); in t4_hw_pci_read_cfg4()
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); in t4_hw_pci_read_cfg4()
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
183 static void t4_report_fw_error(struct adapter *adap) in t4_report_fw_error() argument
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_report_fw_error()
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", in t4_report_fw_error()
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, in get_mbox_rpl() argument
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); in get_mbox_rpl()
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr) in fw_asrt() argument
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); in fw_asrt()
221 dev_alert(adap->pdev_dev, in fw_asrt()
227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) in dump_mbox() argument
229 dev_err(adap->pdev_dev, in dump_mbox()
231 (unsigned long long)t4_read_reg64(adap, data_reg), in dump_mbox()
232 (unsigned long long)t4_read_reg64(adap, data_reg + 8), in dump_mbox()
233 (unsigned long long)t4_read_reg64(adap, data_reg + 16), in dump_mbox()
234 (unsigned long long)t4_read_reg64(adap, data_reg + 24), in dump_mbox()
235 (unsigned long long)t4_read_reg64(adap, data_reg + 32), in dump_mbox()
236 (unsigned long long)t4_read_reg64(adap, data_reg + 40), in dump_mbox()
237 (unsigned long long)t4_read_reg64(adap, data_reg + 48), in dump_mbox()
238 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); in dump_mbox()
264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, in t4_wr_mbox_meat_timeout() argument
285 if (adap->pdev->error_state != pci_channel_io_normal) in t4_wr_mbox_meat_timeout()
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); in t4_wr_mbox_meat_timeout()
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); in t4_wr_mbox_meat_timeout()
299 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat_timeout()
313 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
316 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
320 res = t4_read_reg64(adap, data_reg); in t4_wr_mbox_meat_timeout()
322 fw_asrt(adap, data_reg); in t4_wr_mbox_meat_timeout()
325 get_mbox_rpl(adap, rpl, size / 8, data_reg); in t4_wr_mbox_meat_timeout()
329 dump_mbox(adap, mbox, data_reg); in t4_wr_mbox_meat_timeout()
330 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
335 dump_mbox(adap, mbox, data_reg); in t4_wr_mbox_meat_timeout()
336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", in t4_wr_mbox_meat_timeout()
338 t4_report_fw_error(adap); in t4_wr_mbox_meat_timeout()
342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, in t4_wr_mbox_meat() argument
345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok, in t4_wr_mbox_meat()
349 static int t4_edc_err_read(struct adapter *adap, int idx) in t4_edc_err_read() argument
354 if (is_t4(adap->params.chip)) { in t4_edc_err_read()
355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); in t4_edc_err_read()
359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); in t4_edc_err_read()
366 CH_WARN(adap, in t4_edc_err_read()
369 t4_read_reg(adap, edc_ecc_err_addr_reg)); in t4_edc_err_read()
370 CH_WARN(adap, in t4_edc_err_read()
373 (unsigned long long)t4_read_reg64(adap, rdata_reg), in t4_edc_err_read()
374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8), in t4_edc_err_read()
375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16), in t4_edc_err_read()
376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24), in t4_edc_err_read()
377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32), in t4_edc_err_read()
378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40), in t4_edc_err_read()
379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48), in t4_edc_err_read()
380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56), in t4_edc_err_read()
381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64)); in t4_edc_err_read()
403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, in t4_memory_rw() argument
430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); in t4_memory_rw()
434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, in t4_memory_rw()
450 mem_reg = t4_read_reg(adap, in t4_memory_rw()
455 if (is_t4(adap->params.chip)) in t4_memory_rw()
456 mem_base -= adap->t4_bar0; in t4_memory_rw()
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); in t4_memory_rw()
469 t4_write_reg(adap, in t4_memory_rw()
472 t4_read_reg(adap, in t4_memory_rw()
511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, in t4_memory_rw()
514 t4_write_reg(adap, mem_base + offset, in t4_memory_rw()
528 t4_write_reg(adap, in t4_memory_rw()
531 t4_read_reg(adap, in t4_memory_rw()
552 (__force __le32)t4_read_reg(adap, in t4_memory_rw()
560 t4_write_reg(adap, mem_base + offset, in t4_memory_rw()
573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg) in t4_read_pcie_cfg4() argument
592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf)); in t4_read_pcie_cfg4()
598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), in t4_read_pcie_cfg4()
606 t4_hw_pci_read_cfg4(adap, reg, &val); in t4_read_pcie_cfg4()
614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask, in t4_get_window() argument
619 if (is_t4(adap->params.chip)) { in t4_get_window()
631 bar0 = t4_read_pcie_cfg4(adap, pci_base); in t4_get_window()
633 adap->t4_bar0 = bar0; in t4_get_window()
644 u32 t4_get_util_window(struct adapter *adap) in t4_get_util_window() argument
646 return t4_get_window(adap, PCI_BASE_ADDRESS_0, in t4_get_util_window()
654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window) in t4_setup_memwin() argument
656 t4_write_reg(adap, in t4_setup_memwin()
660 t4_read_reg(adap, in t4_setup_memwin()
698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) in t4_get_regs() argument
2507 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
2529 dev_err(adap->pdev_dev, in t4_get_regs()
2547 *bufp++ = t4_read_reg(adap, reg); in t4_get_regs()
2947 int t4_get_exprom_version(struct adapter *adap, u32 *vers) in t4_get_exprom_version() argument
2957 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, in t4_get_exprom_version()
2982 int t4_check_fw_version(struct adapter *adap) in t4_check_fw_version() argument
2986 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_check_fw_version()
2988 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
2991 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
2996 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers); in t4_check_fw_version()
2997 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers); in t4_check_fw_version()
2998 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers); in t4_check_fw_version()
3017 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n", in t4_check_fw_version()
3018 adap->chip); in t4_check_fw_version()
3024 dev_err(adap->pdev_dev, in t4_check_fw_version()
3056 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable, in should_install_fs_fw() argument
3074 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " in should_install_fs_fw()
3084 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, in t4_prep_fw() argument
3096 ret = -t4_read_flash(adap, FLASH_FW_START, in t4_prep_fw()
3102 dev_err(adap->pdev_dev, in t4_prep_fw()
3122 should_install_fs_fw(adap, card_fw_usable, in t4_prep_fw()
3125 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data, in t4_prep_fw()
3128 dev_err(adap->pdev_dev, in t4_prep_fw()
3146 dev_err(adap->pdev_dev, "Cannot find a usable firmware: " in t4_prep_fw()
3162 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
3163 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in t4_prep_fw()
3220 static bool t4_fw_matches_chip(const struct adapter *adap, in t4_fw_matches_chip() argument
3226 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
3227 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || in t4_fw_matches_chip()
3228 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) in t4_fw_matches_chip()
3231 dev_err(adap->pdev_dev, in t4_fw_matches_chip()
3233 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); in t4_fw_matches_chip()
3245 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) in t4_load_fw() argument
3253 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
3254 unsigned int fw_img_start = adap->params.sf_fw_start; in t4_load_fw()
3258 dev_err(adap->pdev_dev, "FW image has no data\n"); in t4_load_fw()
3262 dev_err(adap->pdev_dev, in t4_load_fw()
3267 dev_err(adap->pdev_dev, in t4_load_fw()
3272 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", in t4_load_fw()
3276 if (!t4_fw_matches_chip(adap, hdr)) in t4_load_fw()
3283 dev_err(adap->pdev_dev, in t4_load_fw()
3289 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); in t4_load_fw()
3300 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); in t4_load_fw()
3308 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); in t4_load_fw()
3313 ret = t4_write_flash(adap, in t4_load_fw()
3318 dev_err(adap->pdev_dev, "firmware download failed, error %d\n", in t4_load_fw()
3321 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_load_fw()
3333 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver) in t4_phy_fw_ver() argument
3340 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_phy_fw_ver()
3342 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, in t4_phy_fw_ver()
3377 int t4_load_phy_fw(struct adapter *adap, in t4_load_phy_fw() argument
3392 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); in t4_load_phy_fw()
3397 CH_WARN(adap, "PHY Firmware already up-to-date, " in t4_load_phy_fw()
3411 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3414 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3426 ret = t4_memory_rw(adap, win, mtype, maddr, in t4_load_phy_fw()
3441 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3443 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3450 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); in t4_load_phy_fw()
3455 CH_WARN(adap, "PHY Firmware did not update: " in t4_load_phy_fw()
3471 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) in t4_fwcache() argument
3479 FW_PARAMS_CMD_PFN_V(adap->pf) | in t4_fwcache()
3487 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); in t4_fwcache()
3490 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, in t4_cim_read_pif_la() argument
3497 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); in t4_cim_read_pif_la()
3499 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); in t4_cim_read_pif_la()
3501 val = t4_read_reg(adap, CIM_DEBUGSTS_A); in t4_cim_read_pif_la()
3511 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) | in t4_cim_read_pif_la()
3513 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A); in t4_cim_read_pif_la()
3514 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A); in t4_cim_read_pif_la()
3521 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); in t4_cim_read_pif_la()
3524 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) in t4_cim_read_ma_la() argument
3529 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); in t4_cim_read_ma_la()
3531 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); in t4_cim_read_ma_la()
3536 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) | in t4_cim_read_ma_la()
3538 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A); in t4_cim_read_ma_la()
3539 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A); in t4_cim_read_ma_la()
3542 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); in t4_cim_read_ma_la()
3545 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) in t4_ulprx_read_la() argument
3552 t4_write_reg(adap, ULP_RX_LA_CTL_A, i); in t4_ulprx_read_la()
3553 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); in t4_ulprx_read_la()
3554 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); in t4_ulprx_read_la()
3556 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); in t4_ulprx_read_la()
3577 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, in t4_link_l1cfg() argument
3607 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_link_l1cfg()
3618 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) in t4_restart_aneg() argument
3630 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_restart_aneg()
3633 typedef void (*int_handler_t)(struct adapter *adap);
4053 static void le_intr_handler(struct adapter *adap) in le_intr_handler() argument
4055 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); in le_intr_handler()
4074 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, in le_intr_handler()
4077 t4_fatal_err(adap); in le_intr_handler()
4205 static void ma_intr_handler(struct adapter *adap) in ma_intr_handler() argument
4207 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); in ma_intr_handler()
4210 dev_alert(adap->pdev_dev, in ma_intr_handler()
4212 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); in ma_intr_handler()
4213 if (is_t5(adap->params.chip)) in ma_intr_handler()
4214 dev_alert(adap->pdev_dev, in ma_intr_handler()
4216 t4_read_reg(adap, in ma_intr_handler()
4220 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); in ma_intr_handler()
4221 dev_alert(adap->pdev_dev, "MA address wrap-around error by " in ma_intr_handler()
4226 t4_write_reg(adap, MA_INT_CAUSE_A, status); in ma_intr_handler()
4227 t4_fatal_err(adap); in ma_intr_handler()
4233 static void smb_intr_handler(struct adapter *adap) in smb_intr_handler() argument
4242 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info)) in smb_intr_handler()
4243 t4_fatal_err(adap); in smb_intr_handler()
4249 static void ncsi_intr_handler(struct adapter *adap) in ncsi_intr_handler() argument
4259 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info)) in ncsi_intr_handler()
4260 t4_fatal_err(adap); in ncsi_intr_handler()
4266 static void xgmac_intr_handler(struct adapter *adap, int port) in xgmac_intr_handler() argument
4270 if (is_t4(adap->params.chip)) in xgmac_intr_handler()
4275 v = t4_read_reg(adap, int_cause_reg); in xgmac_intr_handler()
4282 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", in xgmac_intr_handler()
4285 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", in xgmac_intr_handler()
4287 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); in xgmac_intr_handler()
4288 t4_fatal_err(adap); in xgmac_intr_handler()
4294 static void pl_intr_handler(struct adapter *adap) in pl_intr_handler() argument
4302 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info)) in pl_intr_handler()
4303 t4_fatal_err(adap); in pl_intr_handler()
4568 static int rd_rss_row(struct adapter *adap, int row, u32 *val) in rd_rss_row() argument
4570 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); in rd_rss_row()
4571 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1, in rd_rss_row()
4597 static unsigned int t4_use_ldst(struct adapter *adap) in t4_use_ldst() argument
4599 return (adap->flags & FW_OK) || !adap->use_bd; in t4_use_ldst()
4612 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, in t4_fw_tp_pio_rw() argument
4630 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); in t4_fw_tp_pio_rw()
4643 void t4_read_rss_key(struct adapter *adap, u32 *key) in t4_read_rss_key() argument
4645 if (t4_use_ldst(adap)) in t4_read_rss_key()
4646 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1); in t4_read_rss_key()
4648 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, in t4_read_rss_key()
4662 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) in t4_write_rss_key() argument
4665 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A); in t4_write_rss_key()
4671 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && in t4_write_rss_key()
4675 if (t4_use_ldst(adap)) in t4_write_rss_key()
4676 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0); in t4_write_rss_key()
4678 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, in t4_write_rss_key()
4683 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, in t4_write_rss_key()
4687 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, in t4_write_rss_key()
4800 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, in t4_tp_get_tcp_stats() argument
4810 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_tp_get_tcp_stats()
4818 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_tp_get_tcp_stats()
4837 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) in t4_tp_get_err_stats() argument
4839 int nchan = adap->params.arch.nchan; in t4_tp_get_err_stats()
4841 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4843 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4845 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4847 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4849 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4851 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4853 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4855 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4858 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
4869 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) in t4_tp_get_cpl_stats() argument
4871 int nchan = adap->params.arch.nchan; in t4_tp_get_cpl_stats()
4873 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req, in t4_tp_get_cpl_stats()
4875 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp, in t4_tp_get_cpl_stats()
4887 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st) in t4_tp_get_rdma_stats() argument
4889 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt, in t4_tp_get_rdma_stats()
4901 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, in t4_get_fcoe_stats() argument
4906 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp, in t4_get_fcoe_stats()
4908 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop, in t4_get_fcoe_stats()
4910 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_get_fcoe_stats()
4922 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st) in t4_get_usm_stats() argument
4926 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4, in t4_get_usm_stats()
4941 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) in t4_read_mtu_tbl() argument
4947 t4_write_reg(adap, TP_MTU_TABLE_A, in t4_read_mtu_tbl()
4949 v = t4_read_reg(adap, TP_MTU_TABLE_A); in t4_read_mtu_tbl()
4964 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) in t4_read_cong_tbl() argument
4970 t4_write_reg(adap, TP_CCTRL_TABLE_A, in t4_read_cong_tbl()
4972 incr[mtu][w] = (u16)t4_read_reg(adap, in t4_read_cong_tbl()
4986 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, in t4_tp_wr_bits_indirect() argument
4989 t4_write_reg(adap, TP_PIO_ADDR_A, addr); in t4_tp_wr_bits_indirect()
4990 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; in t4_tp_wr_bits_indirect()
4991 t4_write_reg(adap, TP_PIO_DATA_A, val); in t4_tp_wr_bits_indirect()
5053 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, in t4_load_mtus() argument
5070 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | in t4_load_mtus()
5079 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | in t4_load_mtus()
5094 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) in chan_rate() argument
5096 u64 v = bytes256 * adap->params.vpd.cclk; in chan_rate()
5110 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) in t4_get_chan_txrate() argument
5114 v = t4_read_reg(adap, TP_TX_TRATE_A); in t4_get_chan_txrate()
5115 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v)); in t4_get_chan_txrate()
5116 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v)); in t4_get_chan_txrate()
5117 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5118 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v)); in t4_get_chan_txrate()
5119 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v)); in t4_get_chan_txrate()
5122 v = t4_read_reg(adap, TP_TX_ORATE_A); in t4_get_chan_txrate()
5123 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v)); in t4_get_chan_txrate()
5124 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v)); in t4_get_chan_txrate()
5125 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5126 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v)); in t4_get_chan_txrate()
5127 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v)); in t4_get_chan_txrate()
5142 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, in t4_set_trace_filter() argument
5150 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); in t4_set_trace_filter()
5154 cfg = t4_read_reg(adap, MPS_TRC_CFG_A); in t4_set_trace_filter()
5172 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 || in t4_set_trace_filter()
5178 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); in t4_set_trace_filter()
5185 t4_write_reg(adap, data_reg, tp->data[i]); in t4_set_trace_filter()
5186 t4_write_reg(adap, mask_reg, ~tp->mask[i]); in t4_set_trace_filter()
5188 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst, in t4_set_trace_filter()
5191 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, in t4_set_trace_filter()
5193 (is_t4(adap->params.chip) ? in t4_set_trace_filter()
5210 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, in t4_get_trace_filter() argument
5217 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst); in t4_get_trace_filter()
5218 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst); in t4_get_trace_filter()
5220 if (is_t4(adap->params.chip)) { in t4_get_trace_filter()
5239 tp->mask[i] = ~t4_read_reg(adap, mask_reg); in t4_get_trace_filter()
5240 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; in t4_get_trace_filter()
5252 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmtx_get_stats() argument
5258 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); in t4_pmtx_get_stats()
5259 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); in t4_pmtx_get_stats()
5260 if (is_t4(adap->params.chip)) { in t4_pmtx_get_stats()
5261 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A); in t4_pmtx_get_stats()
5263 t4_read_indirect(adap, PM_TX_DBG_CTRL_A, in t4_pmtx_get_stats()
5279 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmrx_get_stats() argument
5285 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); in t4_pmrx_get_stats()
5286 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); in t4_pmrx_get_stats()
5287 if (is_t4(adap->params.chip)) { in t4_pmrx_get_stats()
5288 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A); in t4_pmrx_get_stats()
5290 t4_read_indirect(adap, PM_RX_DBG_CTRL_A, in t4_pmrx_get_stats()
5307 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) in t4_get_mps_bg_map() argument
5309 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); in t4_get_mps_bg_map()
5356 void t4_get_port_stats_offset(struct adapter *adap, int idx, in t4_get_port_stats_offset() argument
5363 t4_get_port_stats(adap, idx, stats); in t4_get_port_stats_offset()
5378 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) in t4_get_port_stats() argument
5380 u32 bgmap = t4_get_mps_bg_map(adap, idx); in t4_get_port_stats()
5383 t4_read_reg64(adap, \ in t4_get_port_stats()
5384 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
5386 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) in t4_get_port_stats()
5461 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) in t4_get_lb_stats() argument
5463 u32 bgmap = t4_get_mps_bg_map(adap, idx); in t4_get_lb_stats()
5466 t4_read_reg64(adap, \ in t4_get_lb_stats()
5467 (is_t4(adap->params.chip) ? \ in t4_get_lb_stats()
5470 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) in t4_get_lb_stats()
5529 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, in t4_fwaddrspace_write() argument
5545 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fwaddrspace_write()
5559 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, in t4_mdio_rd() argument
5576 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_mdio_rd()
5593 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, in t4_mdio_wr() argument
5610 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_mdio_wr()
5727 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) in t4_sge_ctxt_flush() argument
5741 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_sge_ctxt_flush()
5756 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, in t4_fw_hello() argument
5784 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_fw_hello()
5788 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) in t4_fw_hello()
5789 t4_report_fw_error(adap); in t4_fw_hello()
5838 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_fw_hello()
5882 int t4_fw_bye(struct adapter *adap, unsigned int mbox) in t4_fw_bye() argument
5888 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_bye()
5899 int t4_early_init(struct adapter *adap, unsigned int mbox) in t4_early_init() argument
5905 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_early_init()
5916 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) in t4_fw_reset() argument
5923 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_reset()
5942 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) in t4_fw_halt() argument
5957 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_halt()
5974 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); in t4_fw_halt()
5975 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, in t4_fw_halt()
6007 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) in t4_fw_restart() argument
6015 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0); in t4_fw_restart()
6025 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); in t4_fw_restart()
6027 if (t4_fw_reset(adap, mbox, in t4_fw_restart()
6032 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); in t4_fw_restart()
6037 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); in t4_fw_restart()
6039 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) in t4_fw_restart()
6070 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, in t4_fw_upgrade() argument
6076 if (!t4_fw_matches_chip(adap, fw_hdr)) in t4_fw_upgrade()
6079 ret = t4_fw_halt(adap, mbox, force); in t4_fw_upgrade()
6083 ret = t4_load_fw(adap, fw_data, size); in t4_fw_upgrade()
6096 return t4_fw_restart(adap, mbox, reset); in t4_fw_upgrade()
6109 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, in t4_fixup_host_params() argument
6118 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, in t4_fixup_host_params()
6128 if (is_t4(adap->params.chip)) { in t4_fixup_host_params()
6129 t4_set_reg_field(adap, SGE_CONTROL_A, in t4_fixup_host_params()
6164 t4_set_reg_field(adap, SGE_CONTROL_A, in t4_fixup_host_params()
6169 t4_set_reg_field(adap, SGE_CONTROL2_A, in t4_fixup_host_params()
6195 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); in t4_fixup_host_params()
6196 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, in t4_fixup_host_params()
6197 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) in t4_fixup_host_params()
6199 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, in t4_fixup_host_params()
6200 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) in t4_fixup_host_params()
6203 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); in t4_fixup_host_params()
6216 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) in t4_fw_initialize() argument
6222 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_initialize()
6239 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_query_params_rw() argument
6264 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_query_params_rw()
6271 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_query_params() argument
6275 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); in t4_query_params()
6292 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, in t4_set_params_timeout() argument
6315 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); in t4_set_params_timeout()
6331 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_set_params() argument
6335 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, in t4_set_params()
6360 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_cfg_pfvf() argument
6384 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_cfg_pfvf()
6404 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, in t4_alloc_vi() argument
6419 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_alloc_vi()
6451 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_free_vi() argument
6465 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_free_vi()
6482 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_set_rxmode() argument
6511 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); in t4_set_rxmode()
6536 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, in t4_alloc_mac_filt() argument
6543 unsigned int max_naddr = adap->params.arch.mps_tcam_size; in t4_alloc_mac_filt()
6580 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_mac_filt()
6627 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_change_mac() argument
6633 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; in t4_change_mac()
6649 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_change_mac()
6669 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_set_addr_hash() argument
6682 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); in t4_set_addr_hash()
6697 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, in t4_enable_vi_params() argument
6710 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); in t4_enable_vi_params()
6723 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_enable_vi() argument
6726 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); in t4_enable_vi()
6738 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_identify_port() argument
6749 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_identify_port()
6765 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_iq_free() argument
6780 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_iq_free()
6793 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_eth_eq_free() argument
6805 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_eth_eq_free()
6818 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_ctrl_eq_free() argument
6830 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_ctrl_eq_free()
6843 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_ofld_eq_free() argument
6855 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_ofld_eq_free()
6865 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) in t4_handle_fw_rpl() argument
6873 int port = adap->chan_map[chan]; in t4_handle_fw_rpl()
6874 struct port_info *pi = adap2pinfo(adap, port); in t4_handle_fw_rpl()
6899 t4_os_link_changed(adap, port, link_ok); in t4_handle_fw_rpl()
6903 t4_os_portmod_changed(adap, port); in t4_handle_fw_rpl()
6964 static int get_flash_params(struct adapter *adap) in get_flash_params() argument
6976 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); in get_flash_params()
6978 ret = sf1_read(adap, 3, 0, 1, &info); in get_flash_params()
6979 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ in get_flash_params()
6985 adap->params.sf_size = supported_flash[ret].size_mb; in get_flash_params()
6986 adap->params.sf_nsec = in get_flash_params()
6987 adap->params.sf_size / SF_SEC_SIZE; in get_flash_params()
6995 adap->params.sf_nsec = 1 << (info - 16); in get_flash_params()
6997 adap->params.sf_nsec = 64; in get_flash_params()
7000 adap->params.sf_size = 1 << info; in get_flash_params()
7001 adap->params.sf_fw_start = in get_flash_params()
7002 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; in get_flash_params()
7004 if (adap->params.sf_size < FLASH_MIN_SIZE) in get_flash_params()
7005 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n", in get_flash_params()
7006 adap->params.sf_size, FLASH_MIN_SIZE); in get_flash_params()
7201 int t4_init_devlog_params(struct adapter *adap) in t4_init_devlog_params() argument
7203 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
7214 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG)); in t4_init_devlog_params()
7234 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), in t4_init_devlog_params()
7285 int t4_init_tp_params(struct adapter *adap) in t4_init_tp_params() argument
7290 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); in t4_init_tp_params()
7291 adap->params.tp.tre = TIMERRESOLUTION_G(v); in t4_init_tp_params()
7292 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); in t4_init_tp_params()
7296 adap->params.tp.tx_modq[chan] = chan; in t4_init_tp_params()
7301 if (t4_use_ldst(adap)) { in t4_init_tp_params()
7302 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
7304 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
7307 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, in t4_init_tp_params()
7308 &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
7310 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, in t4_init_tp_params()
7311 &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
7319 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); in t4_init_tp_params()
7320 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); in t4_init_tp_params()
7321 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); in t4_init_tp_params()
7322 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
7328 if ((adap->params.tp.ingress_config & VNIC_F) == 0) in t4_init_tp_params()
7329 adap->params.tp.vnic_shift = -1; in t4_init_tp_params()
7343 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) in t4_filter_field_shift() argument
7345 unsigned int filter_mode = adap->params.tp.vlan_pri_map; in t4_filter_field_shift()
7389 int t4_init_rss_mode(struct adapter *adap, int mbox) in t4_init_rss_mode() argument
7396 for_each_port(adap, i) { in t4_init_rss_mode()
7397 struct port_info *p = adap2pinfo(adap, i); in t4_init_rss_mode()
7404 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); in t4_init_rss_mode()
7412 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) in t4_port_init() argument
7422 for_each_port(adap, i) { in t4_port_init()
7424 struct port_info *p = adap2pinfo(adap, i); in t4_port_init()
7426 while ((adap->params.portvec & (1 << j)) == 0) in t4_port_init()
7435 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_port_init()
7439 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); in t4_port_init()
7447 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); in t4_port_init()
7448 adap->port[i]->dev_port = j; in t4_port_init()
7461 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); in t4_port_init()
7482 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) in t4_read_cimq_cfg() argument
7485 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cimq_cfg()
7489 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | in t4_read_cimq_cfg()
7491 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
7498 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cimq_cfg()
7500 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
7518 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) in t4_read_cim_ibq() argument
7537 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | in t4_read_cim_ibq()
7539 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0, in t4_read_cim_ibq()
7543 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); in t4_read_cim_ibq()
7545 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); in t4_read_cim_ibq()
7560 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) in t4_read_cim_obq() argument
7564 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cim_obq()
7570 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cim_obq()
7572 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cim_obq()
7580 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | in t4_read_cim_obq()
7582 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, in t4_read_cim_obq()
7586 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); in t4_read_cim_obq()
7588 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); in t4_read_cim_obq()
7601 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_read() argument
7606 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_read()
7610 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); in t4_cim_read()
7611 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, in t4_cim_read()
7614 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); in t4_cim_read()
7628 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_write() argument
7633 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_write()
7637 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); in t4_cim_write()
7638 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); in t4_cim_write()
7639 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, in t4_cim_write()
7645 static int t4_cim_write1(struct adapter *adap, unsigned int addr, in t4_cim_write1() argument
7648 return t4_cim_write(adap, addr, 1, &val); in t4_cim_write1()
7661 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) in t4_cim_read_la() argument
7666 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); in t4_cim_read_la()
7671 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0); in t4_cim_read_la()
7676 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); in t4_cim_read_la()
7684 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
7685 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, in t4_cim_read_la()
7689 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); in t4_cim_read_la()
7696 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); in t4_cim_read_la()
7703 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, in t4_cim_read_la()
7721 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) in t4_tp_read_la() argument
7726 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; in t4_tp_read_la()
7728 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
7729 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); in t4_tp_read_la()
7731 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); in t4_tp_read_la()
7741 val |= adap->params.tp.la_mask; in t4_tp_read_la()
7744 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); in t4_tp_read_la()
7745 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A); in t4_tp_read_la()
7754 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
7755 cfg | adap->params.tp.la_mask); in t4_tp_read_la()