Lines Matching refs:reg_addr
3999 u32 reg_addr; in bnx2x_attn_int_asserted() local
4081 reg_addr = (HC_REG_COMMAND_REG + port*32 + in bnx2x_attn_int_asserted()
4084 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); in bnx2x_attn_int_asserted()
4087 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_asserted()
4088 REG_WR(bp, reg_addr, asserted); in bnx2x_attn_int_asserted()
5091 u32 reg_addr; in bnx2x_attn_int_deasserted() local
5155 reg_addr = (HC_REG_COMMAND_REG + port*32 + in bnx2x_attn_int_deasserted()
5158 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); in bnx2x_attn_int_deasserted()
5162 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_deasserted()
5163 REG_WR(bp, reg_addr, val); in bnx2x_attn_int_deasserted()
5168 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : in bnx2x_attn_int_deasserted()
5172 aeu_mask = REG_RD(bp, reg_addr); in bnx2x_attn_int_deasserted()
5179 REG_WR(bp, reg_addr, aeu_mask); in bnx2x_attn_int_deasserted()
7707 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : in bnx2x_init_hw_port() local
7709 val = REG_RD(bp, reg_addr); in bnx2x_init_hw_port()
7711 REG_WR(bp, reg_addr, val); in bnx2x_init_hw_port()