Lines Matching refs:pdata
128 static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata) in xgbe_an_enable_kr_training() argument
132 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); in xgbe_an_enable_kr_training()
135 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); in xgbe_an_enable_kr_training()
138 static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata) in xgbe_an_disable_kr_training() argument
142 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); in xgbe_an_disable_kr_training()
145 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); in xgbe_an_disable_kr_training()
148 static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata) in xgbe_pcs_power_cycle() argument
152 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_pcs_power_cycle()
155 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_pcs_power_cycle()
160 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_pcs_power_cycle()
163 static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata) in xgbe_serdes_start_ratechange() argument
166 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1); in xgbe_serdes_start_ratechange()
169 static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata) in xgbe_serdes_complete_ratechange() argument
175 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0); in xgbe_serdes_complete_ratechange()
182 status = XSIR0_IOREAD(pdata, SIR0_STATUS); in xgbe_serdes_complete_ratechange()
188 netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n", in xgbe_serdes_complete_ratechange()
193 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0); in xgbe_serdes_complete_ratechange()
194 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1); in xgbe_serdes_complete_ratechange()
197 static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata) in xgbe_xgmii_mode() argument
202 xgbe_an_enable_kr_training(pdata); in xgbe_xgmii_mode()
205 pdata->hw_if.set_xgmii_speed(pdata); in xgbe_xgmii_mode()
208 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_xgmii_mode()
211 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_xgmii_mode()
213 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_xgmii_mode()
216 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_xgmii_mode()
218 xgbe_pcs_power_cycle(pdata); in xgbe_xgmii_mode()
221 xgbe_serdes_start_ratechange(pdata); in xgbe_xgmii_mode()
223 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE); in xgbe_xgmii_mode()
224 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD); in xgbe_xgmii_mode()
225 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL); in xgbe_xgmii_mode()
227 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, in xgbe_xgmii_mode()
228 pdata->serdes_cdr_rate[XGBE_SPEED_10000]); in xgbe_xgmii_mode()
229 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, in xgbe_xgmii_mode()
230 pdata->serdes_tx_amp[XGBE_SPEED_10000]); in xgbe_xgmii_mode()
231 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, in xgbe_xgmii_mode()
232 pdata->serdes_blwc[XGBE_SPEED_10000]); in xgbe_xgmii_mode()
233 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, in xgbe_xgmii_mode()
234 pdata->serdes_pq_skew[XGBE_SPEED_10000]); in xgbe_xgmii_mode()
235 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, in xgbe_xgmii_mode()
236 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]); in xgbe_xgmii_mode()
237 XRXTX_IOWRITE(pdata, RXTX_REG22, in xgbe_xgmii_mode()
238 pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]); in xgbe_xgmii_mode()
240 xgbe_serdes_complete_ratechange(pdata); in xgbe_xgmii_mode()
242 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); in xgbe_xgmii_mode()
245 static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata) in xgbe_gmii_2500_mode() argument
250 xgbe_an_disable_kr_training(pdata); in xgbe_gmii_2500_mode()
253 pdata->hw_if.set_gmii_2500_speed(pdata); in xgbe_gmii_2500_mode()
256 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_gmii_2500_mode()
259 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_gmii_2500_mode()
261 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_gmii_2500_mode()
264 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_gmii_2500_mode()
266 xgbe_pcs_power_cycle(pdata); in xgbe_gmii_2500_mode()
269 xgbe_serdes_start_ratechange(pdata); in xgbe_gmii_2500_mode()
271 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE); in xgbe_gmii_2500_mode()
272 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD); in xgbe_gmii_2500_mode()
273 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL); in xgbe_gmii_2500_mode()
275 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, in xgbe_gmii_2500_mode()
276 pdata->serdes_cdr_rate[XGBE_SPEED_2500]); in xgbe_gmii_2500_mode()
277 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, in xgbe_gmii_2500_mode()
278 pdata->serdes_tx_amp[XGBE_SPEED_2500]); in xgbe_gmii_2500_mode()
279 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, in xgbe_gmii_2500_mode()
280 pdata->serdes_blwc[XGBE_SPEED_2500]); in xgbe_gmii_2500_mode()
281 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, in xgbe_gmii_2500_mode()
282 pdata->serdes_pq_skew[XGBE_SPEED_2500]); in xgbe_gmii_2500_mode()
283 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, in xgbe_gmii_2500_mode()
284 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]); in xgbe_gmii_2500_mode()
285 XRXTX_IOWRITE(pdata, RXTX_REG22, in xgbe_gmii_2500_mode()
286 pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]); in xgbe_gmii_2500_mode()
288 xgbe_serdes_complete_ratechange(pdata); in xgbe_gmii_2500_mode()
290 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); in xgbe_gmii_2500_mode()
293 static void xgbe_gmii_mode(struct xgbe_prv_data *pdata) in xgbe_gmii_mode() argument
298 xgbe_an_disable_kr_training(pdata); in xgbe_gmii_mode()
301 pdata->hw_if.set_gmii_speed(pdata); in xgbe_gmii_mode()
304 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_gmii_mode()
307 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_gmii_mode()
309 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_gmii_mode()
312 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_gmii_mode()
314 xgbe_pcs_power_cycle(pdata); in xgbe_gmii_mode()
317 xgbe_serdes_start_ratechange(pdata); in xgbe_gmii_mode()
319 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE); in xgbe_gmii_mode()
320 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD); in xgbe_gmii_mode()
321 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL); in xgbe_gmii_mode()
323 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, in xgbe_gmii_mode()
324 pdata->serdes_cdr_rate[XGBE_SPEED_1000]); in xgbe_gmii_mode()
325 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, in xgbe_gmii_mode()
326 pdata->serdes_tx_amp[XGBE_SPEED_1000]); in xgbe_gmii_mode()
327 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, in xgbe_gmii_mode()
328 pdata->serdes_blwc[XGBE_SPEED_1000]); in xgbe_gmii_mode()
329 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, in xgbe_gmii_mode()
330 pdata->serdes_pq_skew[XGBE_SPEED_1000]); in xgbe_gmii_mode()
331 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, in xgbe_gmii_mode()
332 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]); in xgbe_gmii_mode()
333 XRXTX_IOWRITE(pdata, RXTX_REG22, in xgbe_gmii_mode()
334 pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]); in xgbe_gmii_mode()
336 xgbe_serdes_complete_ratechange(pdata); in xgbe_gmii_mode()
338 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); in xgbe_gmii_mode()
341 static void xgbe_cur_mode(struct xgbe_prv_data *pdata, in xgbe_cur_mode() argument
346 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_cur_mode()
353 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) in xgbe_in_kr_mode() argument
357 xgbe_cur_mode(pdata, &mode); in xgbe_in_kr_mode()
362 static void xgbe_switch_mode(struct xgbe_prv_data *pdata) in xgbe_switch_mode() argument
365 if (xgbe_in_kr_mode(pdata)) { in xgbe_switch_mode()
366 if (pdata->speed_set == XGBE_SPEEDSET_1000_10000) in xgbe_switch_mode()
367 xgbe_gmii_mode(pdata); in xgbe_switch_mode()
369 xgbe_gmii_2500_mode(pdata); in xgbe_switch_mode()
371 xgbe_xgmii_mode(pdata); in xgbe_switch_mode()
375 static void xgbe_set_mode(struct xgbe_prv_data *pdata, in xgbe_set_mode() argument
380 xgbe_cur_mode(pdata, &cur_mode); in xgbe_set_mode()
382 xgbe_switch_mode(pdata); in xgbe_set_mode()
385 static bool xgbe_use_xgmii_mode(struct xgbe_prv_data *pdata) in xgbe_use_xgmii_mode() argument
387 if (pdata->phy.autoneg == AUTONEG_ENABLE) { in xgbe_use_xgmii_mode()
388 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) in xgbe_use_xgmii_mode()
391 if (pdata->phy.speed == SPEED_10000) in xgbe_use_xgmii_mode()
398 static bool xgbe_use_gmii_2500_mode(struct xgbe_prv_data *pdata) in xgbe_use_gmii_2500_mode() argument
400 if (pdata->phy.autoneg == AUTONEG_ENABLE) { in xgbe_use_gmii_2500_mode()
401 if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) in xgbe_use_gmii_2500_mode()
404 if (pdata->phy.speed == SPEED_2500) in xgbe_use_gmii_2500_mode()
411 static bool xgbe_use_gmii_mode(struct xgbe_prv_data *pdata) in xgbe_use_gmii_mode() argument
413 if (pdata->phy.autoneg == AUTONEG_ENABLE) { in xgbe_use_gmii_mode()
414 if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) in xgbe_use_gmii_mode()
417 if (pdata->phy.speed == SPEED_1000) in xgbe_use_gmii_mode()
424 static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart) in xgbe_set_an() argument
428 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_set_an()
437 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_set_an()
440 static void xgbe_restart_an(struct xgbe_prv_data *pdata) in xgbe_restart_an() argument
442 xgbe_set_an(pdata, true, true); in xgbe_restart_an()
444 netif_dbg(pdata, link, pdata->netdev, "AN enabled/restarted\n"); in xgbe_restart_an()
447 static void xgbe_disable_an(struct xgbe_prv_data *pdata) in xgbe_disable_an() argument
449 xgbe_set_an(pdata, false, false); in xgbe_disable_an()
451 netif_dbg(pdata, link, pdata->netdev, "AN disabled\n"); in xgbe_disable_an()
454 static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata, in xgbe_an_tx_training() argument
462 if (!xgbe_in_kr_mode(pdata)) in xgbe_an_tx_training()
466 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_an_tx_training()
467 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_an_tx_training()
469 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); in xgbe_an_tx_training()
472 reg |= pdata->fec_ability; in xgbe_an_tx_training()
474 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); in xgbe_an_tx_training()
477 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); in xgbe_an_tx_training()
479 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1); in xgbe_an_tx_training()
482 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, in xgbe_an_tx_training()
485 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0); in xgbe_an_tx_training()
487 netif_dbg(pdata, link, pdata->netdev, in xgbe_an_tx_training()
494 static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata, in xgbe_an_tx_xnp() argument
504 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); in xgbe_an_tx_xnp()
505 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); in xgbe_an_tx_xnp()
506 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); in xgbe_an_tx_xnp()
511 static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata, in xgbe_an_rx_bpa() argument
518 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_an_rx_bpa()
521 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; in xgbe_an_rx_bpa()
526 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_an_rx_bpa()
527 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_an_rx_bpa()
531 ? xgbe_an_tx_xnp(pdata, state) in xgbe_an_rx_bpa()
532 : xgbe_an_tx_training(pdata, state); in xgbe_an_rx_bpa()
535 static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata, in xgbe_an_rx_xnp() argument
541 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); in xgbe_an_rx_xnp()
542 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); in xgbe_an_rx_xnp()
546 ? xgbe_an_tx_xnp(pdata, state) in xgbe_an_rx_xnp()
547 : xgbe_an_tx_training(pdata, state); in xgbe_an_rx_xnp()
550 static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata) in xgbe_an_page_received() argument
556 if (!pdata->an_start) { in xgbe_an_page_received()
557 pdata->an_start = jiffies; in xgbe_an_page_received()
559 an_timeout = pdata->an_start + in xgbe_an_page_received()
563 pdata->kr_state = XGBE_RX_BPA; in xgbe_an_page_received()
564 pdata->kx_state = XGBE_RX_BPA; in xgbe_an_page_received()
566 pdata->an_start = jiffies; in xgbe_an_page_received()
568 netif_dbg(pdata, link, pdata->netdev, in xgbe_an_page_received()
573 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state in xgbe_an_page_received()
574 : &pdata->kx_state; in xgbe_an_page_received()
578 ret = xgbe_an_rx_bpa(pdata, state); in xgbe_an_page_received()
582 ret = xgbe_an_rx_xnp(pdata, state); in xgbe_an_page_received()
592 static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata) in xgbe_an_incompat_link() argument
595 if (xgbe_in_kr_mode(pdata)) { in xgbe_an_incompat_link()
596 pdata->kr_state = XGBE_RX_ERROR; in xgbe_an_incompat_link()
598 if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) && in xgbe_an_incompat_link()
599 !(pdata->phy.advertising & ADVERTISED_2500baseX_Full)) in xgbe_an_incompat_link()
602 if (pdata->kx_state != XGBE_RX_BPA) in xgbe_an_incompat_link()
605 pdata->kx_state = XGBE_RX_ERROR; in xgbe_an_incompat_link()
607 if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full)) in xgbe_an_incompat_link()
610 if (pdata->kr_state != XGBE_RX_BPA) in xgbe_an_incompat_link()
614 xgbe_disable_an(pdata); in xgbe_an_incompat_link()
616 xgbe_switch_mode(pdata); in xgbe_an_incompat_link()
618 xgbe_restart_an(pdata); in xgbe_an_incompat_link()
625 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; in xgbe_an_isr() local
627 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); in xgbe_an_isr()
630 disable_irq_nosync(pdata->an_irq); in xgbe_an_isr()
632 queue_work(pdata->an_workqueue, &pdata->an_irq_work); in xgbe_an_isr()
639 struct xgbe_prv_data *pdata = container_of(work, in xgbe_an_irq_work() local
646 flush_work(&pdata->an_work); in xgbe_an_irq_work()
647 queue_work(pdata->an_workqueue, &pdata->an_work); in xgbe_an_irq_work()
672 struct xgbe_prv_data *pdata = container_of(work, in xgbe_an_state_machine() local
675 enum xgbe_an cur_state = pdata->an_state; in xgbe_an_state_machine()
678 mutex_lock(&pdata->an_mutex); in xgbe_an_state_machine()
681 int_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); in xgbe_an_state_machine()
687 pdata->an_state = XGBE_AN_PAGE_RECEIVED; in xgbe_an_state_machine()
690 pdata->an_state = XGBE_AN_INCOMPAT_LINK; in xgbe_an_state_machine()
693 pdata->an_state = XGBE_AN_COMPLETE; in xgbe_an_state_machine()
696 pdata->an_state = XGBE_AN_ERROR; in xgbe_an_state_machine()
702 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, int_reg); in xgbe_an_state_machine()
704 pdata->an_result = pdata->an_state; in xgbe_an_state_machine()
707 netif_dbg(pdata, link, pdata->netdev, "AN %s\n", in xgbe_an_state_machine()
708 xgbe_state_as_string(pdata->an_state)); in xgbe_an_state_machine()
710 cur_state = pdata->an_state; in xgbe_an_state_machine()
712 switch (pdata->an_state) { in xgbe_an_state_machine()
714 pdata->an_supported = 0; in xgbe_an_state_machine()
718 pdata->an_state = xgbe_an_page_received(pdata); in xgbe_an_state_machine()
719 pdata->an_supported++; in xgbe_an_state_machine()
723 pdata->an_supported = 0; in xgbe_an_state_machine()
724 pdata->parallel_detect = 0; in xgbe_an_state_machine()
725 pdata->an_state = xgbe_an_incompat_link(pdata); in xgbe_an_state_machine()
729 pdata->parallel_detect = pdata->an_supported ? 0 : 1; in xgbe_an_state_machine()
730 netif_dbg(pdata, link, pdata->netdev, "%s successful\n", in xgbe_an_state_machine()
731 pdata->an_supported ? "Auto negotiation" in xgbe_an_state_machine()
739 pdata->an_state = XGBE_AN_ERROR; in xgbe_an_state_machine()
742 if (pdata->an_state == XGBE_AN_NO_LINK) { in xgbe_an_state_machine()
744 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in xgbe_an_state_machine()
745 } else if (pdata->an_state == XGBE_AN_ERROR) { in xgbe_an_state_machine()
746 netdev_err(pdata->netdev, in xgbe_an_state_machine()
751 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in xgbe_an_state_machine()
754 if (pdata->an_state >= XGBE_AN_COMPLETE) { in xgbe_an_state_machine()
755 pdata->an_result = pdata->an_state; in xgbe_an_state_machine()
756 pdata->an_state = XGBE_AN_READY; in xgbe_an_state_machine()
757 pdata->kr_state = XGBE_RX_BPA; in xgbe_an_state_machine()
758 pdata->kx_state = XGBE_RX_BPA; in xgbe_an_state_machine()
759 pdata->an_start = 0; in xgbe_an_state_machine()
761 netif_dbg(pdata, link, pdata->netdev, "AN result: %s\n", in xgbe_an_state_machine()
762 xgbe_state_as_string(pdata->an_result)); in xgbe_an_state_machine()
765 if (cur_state != pdata->an_state) in xgbe_an_state_machine()
772 enable_irq(pdata->an_irq); in xgbe_an_state_machine()
774 mutex_unlock(&pdata->an_mutex); in xgbe_an_state_machine()
777 static void xgbe_an_init(struct xgbe_prv_data *pdata) in xgbe_an_init() argument
782 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_an_init()
783 if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC) in xgbe_an_init()
788 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); in xgbe_an_init()
791 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_an_init()
792 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) in xgbe_an_init()
797 if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || in xgbe_an_init()
798 (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) in xgbe_an_init()
803 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); in xgbe_an_init()
806 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_an_init()
807 if (pdata->phy.advertising & ADVERTISED_Pause) in xgbe_an_init()
812 if (pdata->phy.advertising & ADVERTISED_Asym_Pause) in xgbe_an_init()
820 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); in xgbe_an_init()
822 netif_dbg(pdata, link, pdata->netdev, "AN initialized\n"); in xgbe_an_init()
825 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) in xgbe_phy_fc_string() argument
827 if (pdata->tx_pause && pdata->rx_pause) in xgbe_phy_fc_string()
829 else if (pdata->rx_pause) in xgbe_phy_fc_string()
831 else if (pdata->tx_pause) in xgbe_phy_fc_string()
853 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) in xgbe_phy_print_status() argument
855 if (pdata->phy.link) in xgbe_phy_print_status()
856 netdev_info(pdata->netdev, in xgbe_phy_print_status()
858 xgbe_phy_speed_string(pdata->phy.speed), in xgbe_phy_print_status()
859 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", in xgbe_phy_print_status()
860 xgbe_phy_fc_string(pdata)); in xgbe_phy_print_status()
862 netdev_info(pdata->netdev, "Link is Down\n"); in xgbe_phy_print_status()
865 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) in xgbe_phy_adjust_link() argument
869 if (pdata->phy.link) { in xgbe_phy_adjust_link()
871 pdata->pause_autoneg = pdata->phy.pause_autoneg; in xgbe_phy_adjust_link()
873 if (pdata->tx_pause != pdata->phy.tx_pause) { in xgbe_phy_adjust_link()
875 pdata->hw_if.config_tx_flow_control(pdata); in xgbe_phy_adjust_link()
876 pdata->tx_pause = pdata->phy.tx_pause; in xgbe_phy_adjust_link()
879 if (pdata->rx_pause != pdata->phy.rx_pause) { in xgbe_phy_adjust_link()
881 pdata->hw_if.config_rx_flow_control(pdata); in xgbe_phy_adjust_link()
882 pdata->rx_pause = pdata->phy.rx_pause; in xgbe_phy_adjust_link()
886 if (pdata->phy_speed != pdata->phy.speed) { in xgbe_phy_adjust_link()
888 pdata->phy_speed = pdata->phy.speed; in xgbe_phy_adjust_link()
891 if (pdata->phy_link != pdata->phy.link) { in xgbe_phy_adjust_link()
893 pdata->phy_link = pdata->phy.link; in xgbe_phy_adjust_link()
895 } else if (pdata->phy_link) { in xgbe_phy_adjust_link()
897 pdata->phy_link = 0; in xgbe_phy_adjust_link()
898 pdata->phy_speed = SPEED_UNKNOWN; in xgbe_phy_adjust_link()
901 if (new_state && netif_msg_link(pdata)) in xgbe_phy_adjust_link()
902 xgbe_phy_print_status(pdata); in xgbe_phy_adjust_link()
905 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) in xgbe_phy_config_fixed() argument
907 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); in xgbe_phy_config_fixed()
910 xgbe_disable_an(pdata); in xgbe_phy_config_fixed()
913 switch (pdata->phy.speed) { in xgbe_phy_config_fixed()
915 xgbe_set_mode(pdata, XGBE_MODE_KR); in xgbe_phy_config_fixed()
920 xgbe_set_mode(pdata, XGBE_MODE_KX); in xgbe_phy_config_fixed()
928 if (pdata->phy.duplex != DUPLEX_FULL) in xgbe_phy_config_fixed()
934 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) in __xgbe_phy_config_aneg() argument
936 set_bit(XGBE_LINK_INIT, &pdata->dev_state); in __xgbe_phy_config_aneg()
937 pdata->link_check = jiffies; in __xgbe_phy_config_aneg()
939 if (pdata->phy.autoneg != AUTONEG_ENABLE) in __xgbe_phy_config_aneg()
940 return xgbe_phy_config_fixed(pdata); in __xgbe_phy_config_aneg()
942 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); in __xgbe_phy_config_aneg()
945 disable_irq(pdata->an_irq); in __xgbe_phy_config_aneg()
948 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) { in __xgbe_phy_config_aneg()
949 xgbe_set_mode(pdata, XGBE_MODE_KR); in __xgbe_phy_config_aneg()
950 } else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || in __xgbe_phy_config_aneg()
951 (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) { in __xgbe_phy_config_aneg()
952 xgbe_set_mode(pdata, XGBE_MODE_KX); in __xgbe_phy_config_aneg()
954 enable_irq(pdata->an_irq); in __xgbe_phy_config_aneg()
959 xgbe_disable_an(pdata); in __xgbe_phy_config_aneg()
962 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in __xgbe_phy_config_aneg()
964 pdata->an_result = XGBE_AN_READY; in __xgbe_phy_config_aneg()
965 pdata->an_state = XGBE_AN_READY; in __xgbe_phy_config_aneg()
966 pdata->kr_state = XGBE_RX_BPA; in __xgbe_phy_config_aneg()
967 pdata->kx_state = XGBE_RX_BPA; in __xgbe_phy_config_aneg()
970 enable_irq(pdata->an_irq); in __xgbe_phy_config_aneg()
973 xgbe_an_init(pdata); in __xgbe_phy_config_aneg()
976 xgbe_restart_an(pdata); in __xgbe_phy_config_aneg()
981 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) in xgbe_phy_config_aneg() argument
985 mutex_lock(&pdata->an_mutex); in xgbe_phy_config_aneg()
987 ret = __xgbe_phy_config_aneg(pdata); in xgbe_phy_config_aneg()
989 set_bit(XGBE_LINK_ERR, &pdata->dev_state); in xgbe_phy_config_aneg()
991 clear_bit(XGBE_LINK_ERR, &pdata->dev_state); in xgbe_phy_config_aneg()
993 mutex_unlock(&pdata->an_mutex); in xgbe_phy_config_aneg()
998 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) in xgbe_phy_aneg_done() argument
1000 return (pdata->an_result == XGBE_AN_COMPLETE); in xgbe_phy_aneg_done()
1003 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) in xgbe_check_link_timeout() argument
1007 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); in xgbe_check_link_timeout()
1009 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); in xgbe_check_link_timeout()
1010 xgbe_phy_config_aneg(pdata); in xgbe_check_link_timeout()
1014 static void xgbe_phy_status_force(struct xgbe_prv_data *pdata) in xgbe_phy_status_force() argument
1016 if (xgbe_in_kr_mode(pdata)) { in xgbe_phy_status_force()
1017 pdata->phy.speed = SPEED_10000; in xgbe_phy_status_force()
1019 switch (pdata->speed_set) { in xgbe_phy_status_force()
1021 pdata->phy.speed = SPEED_1000; in xgbe_phy_status_force()
1025 pdata->phy.speed = SPEED_2500; in xgbe_phy_status_force()
1029 pdata->phy.duplex = DUPLEX_FULL; in xgbe_phy_status_force()
1032 static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) in xgbe_phy_status_aneg() argument
1036 pdata->phy.lp_advertising = 0; in xgbe_phy_status_aneg()
1038 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) in xgbe_phy_status_aneg()
1039 return xgbe_phy_status_force(pdata); in xgbe_phy_status_aneg()
1041 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; in xgbe_phy_status_aneg()
1042 pdata->phy.lp_advertising |= ADVERTISED_Backplane; in xgbe_phy_status_aneg()
1045 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_status_aneg()
1046 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_status_aneg()
1048 pdata->phy.lp_advertising |= ADVERTISED_Pause; in xgbe_phy_status_aneg()
1050 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; in xgbe_phy_status_aneg()
1052 if (pdata->phy.pause_autoneg) { in xgbe_phy_status_aneg()
1054 pdata->phy.tx_pause = 0; in xgbe_phy_status_aneg()
1055 pdata->phy.rx_pause = 0; in xgbe_phy_status_aneg()
1058 pdata->phy.tx_pause = 1; in xgbe_phy_status_aneg()
1059 pdata->phy.rx_pause = 1; in xgbe_phy_status_aneg()
1062 pdata->phy.rx_pause = 1; in xgbe_phy_status_aneg()
1064 pdata->phy.tx_pause = 1; in xgbe_phy_status_aneg()
1069 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_status_aneg()
1070 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_status_aneg()
1072 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; in xgbe_phy_status_aneg()
1074 switch (pdata->speed_set) { in xgbe_phy_status_aneg()
1076 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; in xgbe_phy_status_aneg()
1079 pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full; in xgbe_phy_status_aneg()
1086 pdata->phy.speed = SPEED_10000; in xgbe_phy_status_aneg()
1087 xgbe_set_mode(pdata, XGBE_MODE_KR); in xgbe_phy_status_aneg()
1089 switch (pdata->speed_set) { in xgbe_phy_status_aneg()
1091 pdata->phy.speed = SPEED_1000; in xgbe_phy_status_aneg()
1095 pdata->phy.speed = SPEED_2500; in xgbe_phy_status_aneg()
1099 xgbe_set_mode(pdata, XGBE_MODE_KX); in xgbe_phy_status_aneg()
1101 pdata->phy.speed = SPEED_UNKNOWN; in xgbe_phy_status_aneg()
1105 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_status_aneg()
1106 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_status_aneg()
1108 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; in xgbe_phy_status_aneg()
1110 pdata->phy.duplex = DUPLEX_FULL; in xgbe_phy_status_aneg()
1113 static void xgbe_phy_status(struct xgbe_prv_data *pdata) in xgbe_phy_status() argument
1117 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { in xgbe_phy_status()
1118 netif_carrier_off(pdata->netdev); in xgbe_phy_status()
1120 pdata->phy.link = 0; in xgbe_phy_status()
1124 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); in xgbe_phy_status()
1129 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); in xgbe_phy_status()
1130 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); in xgbe_phy_status()
1131 pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0; in xgbe_phy_status()
1133 if (pdata->phy.link) { in xgbe_phy_status()
1134 if (link_aneg && !xgbe_phy_aneg_done(pdata)) { in xgbe_phy_status()
1135 xgbe_check_link_timeout(pdata); in xgbe_phy_status()
1139 xgbe_phy_status_aneg(pdata); in xgbe_phy_status()
1141 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) in xgbe_phy_status()
1142 clear_bit(XGBE_LINK_INIT, &pdata->dev_state); in xgbe_phy_status()
1144 netif_carrier_on(pdata->netdev); in xgbe_phy_status()
1146 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { in xgbe_phy_status()
1147 xgbe_check_link_timeout(pdata); in xgbe_phy_status()
1153 xgbe_phy_status_aneg(pdata); in xgbe_phy_status()
1155 netif_carrier_off(pdata->netdev); in xgbe_phy_status()
1159 xgbe_phy_adjust_link(pdata); in xgbe_phy_status()
1162 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) in xgbe_phy_stop() argument
1164 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); in xgbe_phy_stop()
1167 xgbe_disable_an(pdata); in xgbe_phy_stop()
1170 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in xgbe_phy_stop()
1172 devm_free_irq(pdata->dev, pdata->an_irq, pdata); in xgbe_phy_stop()
1174 pdata->phy.link = 0; in xgbe_phy_stop()
1175 netif_carrier_off(pdata->netdev); in xgbe_phy_stop()
1177 xgbe_phy_adjust_link(pdata); in xgbe_phy_stop()
1180 static int xgbe_phy_start(struct xgbe_prv_data *pdata) in xgbe_phy_start() argument
1182 struct net_device *netdev = pdata->netdev; in xgbe_phy_start()
1185 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); in xgbe_phy_start()
1187 ret = devm_request_irq(pdata->dev, pdata->an_irq, in xgbe_phy_start()
1188 xgbe_an_isr, 0, pdata->an_name, in xgbe_phy_start()
1189 pdata); in xgbe_phy_start()
1198 if (xgbe_use_xgmii_mode(pdata)) { in xgbe_phy_start()
1199 xgbe_xgmii_mode(pdata); in xgbe_phy_start()
1200 } else if (xgbe_use_gmii_mode(pdata)) { in xgbe_phy_start()
1201 xgbe_gmii_mode(pdata); in xgbe_phy_start()
1202 } else if (xgbe_use_gmii_2500_mode(pdata)) { in xgbe_phy_start()
1203 xgbe_gmii_2500_mode(pdata); in xgbe_phy_start()
1210 xgbe_an_init(pdata); in xgbe_phy_start()
1213 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); in xgbe_phy_start()
1215 return xgbe_phy_config_aneg(pdata); in xgbe_phy_start()
1218 devm_free_irq(pdata->dev, pdata->an_irq, pdata); in xgbe_phy_start()
1223 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) in xgbe_phy_reset() argument
1227 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_reset()
1229 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_reset()
1234 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_reset()
1241 xgbe_disable_an(pdata); in xgbe_phy_reset()
1244 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in xgbe_phy_reset()
1249 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) in xgbe_dump_phy_registers() argument
1251 struct device *dev = pdata->dev; in xgbe_dump_phy_registers()
1256 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); in xgbe_dump_phy_registers()
1258 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); in xgbe_dump_phy_registers()
1260 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); in xgbe_dump_phy_registers()
1262 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); in xgbe_dump_phy_registers()
1264 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); in xgbe_dump_phy_registers()
1266 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); in xgbe_dump_phy_registers()
1269 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); in xgbe_dump_phy_registers()
1271 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); in xgbe_dump_phy_registers()
1274 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); in xgbe_dump_phy_registers()
1277 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); in xgbe_dump_phy_registers()
1280 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); in xgbe_dump_phy_registers()
1283 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); in xgbe_dump_phy_registers()
1288 static void xgbe_phy_init(struct xgbe_prv_data *pdata) in xgbe_phy_init() argument
1290 mutex_init(&pdata->an_mutex); in xgbe_phy_init()
1291 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); in xgbe_phy_init()
1292 INIT_WORK(&pdata->an_work, xgbe_an_state_machine); in xgbe_phy_init()
1293 pdata->mdio_mmd = MDIO_MMD_PCS; in xgbe_phy_init()
1296 pdata->phy.supported = SUPPORTED_Autoneg; in xgbe_phy_init()
1297 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; in xgbe_phy_init()
1298 pdata->phy.supported |= SUPPORTED_Backplane; in xgbe_phy_init()
1299 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; in xgbe_phy_init()
1300 switch (pdata->speed_set) { in xgbe_phy_init()
1302 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; in xgbe_phy_init()
1305 pdata->phy.supported |= SUPPORTED_2500baseX_Full; in xgbe_phy_init()
1309 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, in xgbe_phy_init()
1311 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | in xgbe_phy_init()
1313 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) in xgbe_phy_init()
1314 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; in xgbe_phy_init()
1316 pdata->phy.advertising = pdata->phy.supported; in xgbe_phy_init()
1318 pdata->phy.address = 0; in xgbe_phy_init()
1320 pdata->phy.autoneg = AUTONEG_ENABLE; in xgbe_phy_init()
1321 pdata->phy.speed = SPEED_UNKNOWN; in xgbe_phy_init()
1322 pdata->phy.duplex = DUPLEX_UNKNOWN; in xgbe_phy_init()
1324 pdata->phy.link = 0; in xgbe_phy_init()
1326 pdata->phy.pause_autoneg = pdata->pause_autoneg; in xgbe_phy_init()
1327 pdata->phy.tx_pause = pdata->tx_pause; in xgbe_phy_init()
1328 pdata->phy.rx_pause = pdata->rx_pause; in xgbe_phy_init()
1331 pdata->phy.advertising &= ~ADVERTISED_Pause; in xgbe_phy_init()
1332 pdata->phy.advertising &= ~ADVERTISED_Asym_Pause; in xgbe_phy_init()
1334 if (pdata->rx_pause) { in xgbe_phy_init()
1335 pdata->phy.advertising |= ADVERTISED_Pause; in xgbe_phy_init()
1336 pdata->phy.advertising |= ADVERTISED_Asym_Pause; in xgbe_phy_init()
1339 if (pdata->tx_pause) in xgbe_phy_init()
1340 pdata->phy.advertising ^= ADVERTISED_Asym_Pause; in xgbe_phy_init()
1342 if (netif_msg_drv(pdata)) in xgbe_phy_init()
1343 xgbe_dump_phy_registers(pdata); in xgbe_phy_init()