287 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,  in at91_write()  function
296 	at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));  in set_mb_mode_prio()
333 		at91_write(priv, AT91_MID(i), reg_mid);  in at91_setup_mailboxes()
334 		at91_write(priv, AT91_MCR(i), 0x0);	/* clear dlc */  in at91_setup_mailboxes()
343 		at91_write(priv, AT91_MAM(i), 0x0);  in at91_setup_mailboxes()
344 		at91_write(priv, AT91_MID(i), AT91_MID_MIDE);  in at91_setup_mailboxes()
369 	at91_write(priv, AT91_BR, reg_br);  in at91_set_bittiming()
392 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);  in at91_chip_start()
396 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);  in at91_chip_start()
406 	at91_write(priv, AT91_MR, reg_mr);  in at91_chip_start()
412 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);  in at91_chip_start()
413 	at91_write(priv, AT91_IER, reg_ier);  in at91_chip_start()
422 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);  in at91_chip_stop()
425 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);  in at91_chip_stop()
479 	at91_write(priv, AT91_MID(mb), reg_mid);  in at91_start_xmit()
482 	at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));  in at91_start_xmit()
483 	at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));  in at91_start_xmit()
486 	at91_write(priv, AT91_MCR(mb), reg_mcr);  in at91_start_xmit()
508 	at91_write(priv, AT91_IER, 1 << mb);  in at91_start_xmit()
522 	at91_write(priv, AT91_TCR, mask);  in at91_activate_rx_low()
536 	at91_write(priv, AT91_TCR, mask);  in at91_activate_rx_mb()
597 	at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);  in at91_read_mb()
816 		at91_write(priv, AT91_IER, reg_ier);  in at91_poll()
850 		at91_write(priv, AT91_IDR, 1 << mb);  in at91_irq_tx()
982 	at91_write(priv, AT91_IDR, reg_idr);  in at91_irq_err_state()
983 	at91_write(priv, AT91_IER, reg_ier);  in at91_irq_err_state()
1084 		at91_write(priv, AT91_IDR,  in at91_irq()