221 static int adv7180_write(struct adv7180_state *state, unsigned int reg,  in adv7180_write()  function
447 	ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);  in adv7180_set_power()
498 		ret = adv7180_write(state, ADV7180_REG_BRI, val);  in adv7180_s_ctrl()
502 		ret = adv7180_write(state, ADV7180_REG_HUE, -val);  in adv7180_s_ctrl()
505 		ret = adv7180_write(state, ADV7180_REG_CON, val);  in adv7180_s_ctrl()
512 		ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);  in adv7180_s_ctrl()
515 		ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);  in adv7180_s_ctrl()
520 			adv7180_write(state, 0x80d9, 0x44);  in adv7180_s_ctrl()
521 			adv7180_write(state, ADV7180_REG_FLCONTROL,  in adv7180_s_ctrl()
525 			adv7180_write(state, 0x80d9, 0xc4);  in adv7180_s_ctrl()
526 			adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);  in adv7180_s_ctrl()
753 	adv7180_write(state, ADV7180_REG_ICR3, isr3);  in adv7180_irq()
767 	ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,  in adv7180_init()
773 	return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,  in adv7180_init()
779 	return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,  in adv7180_set_std()
793 	return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);  in adv7180_select_input()
799 		adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,  in adv7182_init()
803 		adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,  in adv7182_init()
808 		adv7180_write(state, 0x0080, 0x51);  in adv7182_init()
809 		adv7180_write(state, 0x0081, 0x51);  in adv7182_init()
810 		adv7180_write(state, 0x0082, 0x68);  in adv7182_init()
815 		adv7180_write(state, 0x0003, 0x4e);  in adv7182_init()
816 		adv7180_write(state, 0x0004, 0x57);  in adv7182_init()
817 		adv7180_write(state, 0x001d, 0xc0);  in adv7182_init()
820 			adv7180_write(state, 0x0004, 0x17);  in adv7182_init()
822 			adv7180_write(state, 0x0004, 0x07);  in adv7182_init()
823 		adv7180_write(state, 0x0003, 0x0c);  in adv7182_init()
824 		adv7180_write(state, 0x001d, 0x40);  in adv7182_init()
827 	adv7180_write(state, 0x0013, 0x00);  in adv7182_init()
834 	return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);  in adv7182_set_std()
896 	ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);  in adv7182_select_input()
901 	adv7180_write(state, 0x809c, 0x00);  in adv7182_select_input()
902 	adv7180_write(state, 0x809c, 0xff);  in adv7182_select_input()
910 		adv7180_write(state, 0x0017, 0x41);  in adv7182_select_input()
913 		adv7180_write(state, 0x0017, 0x01);  in adv7182_select_input()
923 		adv7180_write(state, 0x0052 + i, lbias[i]);  in adv7182_select_input()
927 		adv7180_write(state, 0x005f, 0xa8);  in adv7182_select_input()
928 		adv7180_write(state, 0x005a, 0x90);  in adv7182_select_input()
929 		adv7180_write(state, 0x0060, 0xb0);  in adv7182_select_input()
930 		adv7180_write(state, 0x80b6, 0x08);  in adv7182_select_input()
931 		adv7180_write(state, 0x80c0, 0xa0);  in adv7182_select_input()
933 		adv7180_write(state, 0x005f, 0xf0);  in adv7182_select_input()
934 		adv7180_write(state, 0x005a, 0xd0);  in adv7182_select_input()
935 		adv7180_write(state, 0x0060, 0x10);  in adv7182_select_input()
936 		adv7180_write(state, 0x80b6, 0x9c);  in adv7182_select_input()
937 		adv7180_write(state, 0x80c0, 0x00);  in adv7182_select_input()
1114 	adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);  in init_device()
1130 		ret = adv7180_write(state, ADV7180_REG_ICONF1,  in init_device()
1136 		ret = adv7180_write(state, ADV7180_REG_IMR1, 0);  in init_device()
1140 		ret = adv7180_write(state, ADV7180_REG_IMR2, 0);  in init_device()
1145 		ret = adv7180_write(state, ADV7180_REG_IMR3,  in init_device()
1150 		ret = adv7180_write(state, ADV7180_REG_IMR4, 0);  in init_device()