95 	u32 value;  in tegra_dc_readl_active()  local
100 	value = tegra_dc_readl(dc, offset);  in tegra_dc_readl_active()
104 	return value;  in tegra_dc_readl_active()
244 	unsigned long value, flags;  in tegra_dc_setup_window()  local
259 	value = WINDOW_A_SELECT << index;  in tegra_dc_setup_window()
260 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);  in tegra_dc_setup_window()
265 	value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);  in tegra_dc_setup_window()
266 	tegra_dc_writel(dc, value, DC_WIN_POSITION);  in tegra_dc_setup_window()
268 	value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);  in tegra_dc_setup_window()
269 	tegra_dc_writel(dc, value, DC_WIN_SIZE);  in tegra_dc_setup_window()
276 	value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);  in tegra_dc_setup_window()
277 	tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);  in tegra_dc_setup_window()
289 	value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);  in tegra_dc_setup_window()
290 	tegra_dc_writel(dc, value, DC_WIN_DDA_INC);  in tegra_dc_setup_window()
306 		value = window->stride[1] << 16 | window->stride[0];  in tegra_dc_setup_window()
307 		tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);  in tegra_dc_setup_window()
319 		unsigned long height = window->tiling.value;  in tegra_dc_setup_window()
323 			value = DC_WINBUF_SURFACE_KIND_PITCH;  in tegra_dc_setup_window()
327 			value = DC_WINBUF_SURFACE_KIND_TILED;  in tegra_dc_setup_window()
331 			value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |  in tegra_dc_setup_window()
336 		tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);  in tegra_dc_setup_window()
340 			value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |  in tegra_dc_setup_window()
345 			value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |  in tegra_dc_setup_window()
357 		tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);  in tegra_dc_setup_window()
360 	value = WIN_ENABLE;  in tegra_dc_setup_window()
373 		value |= CSC_ENABLE;  in tegra_dc_setup_window()
375 		value |= COLOR_EXPAND;  in tegra_dc_setup_window()
379 		value |= V_DIRECTION;  in tegra_dc_setup_window()
381 	tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);  in tegra_dc_setup_window()
605 	u32 value;  in tegra_plane_atomic_disable()  local
615 	value = WINDOW_A_SELECT << p->index;  in tegra_plane_atomic_disable()
616 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);  in tegra_plane_atomic_disable()
618 	value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);  in tegra_plane_atomic_disable()
619 	value &= ~WIN_ENABLE;  in tegra_plane_atomic_disable()
620 	tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);  in tegra_plane_atomic_disable()
714 	u32 value = CURSOR_CLIP_DISPLAY;  in tegra_cursor_atomic_update()  local
722 		value |= CURSOR_SIZE_32x32;  in tegra_cursor_atomic_update()
726 		value |= CURSOR_SIZE_64x64;  in tegra_cursor_atomic_update()
730 		value |= CURSOR_SIZE_128x128;  in tegra_cursor_atomic_update()
734 		value |= CURSOR_SIZE_256x256;  in tegra_cursor_atomic_update()
743 	value |= (bo->paddr >> 10) & 0x3fffff;  in tegra_cursor_atomic_update()
744 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);  in tegra_cursor_atomic_update()
747 	value = (bo->paddr >> 32) & 0x3;  in tegra_cursor_atomic_update()
748 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);  in tegra_cursor_atomic_update()
752 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_update()
753 	value |= CURSOR_ENABLE;  in tegra_cursor_atomic_update()
754 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_update()
756 	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);  in tegra_cursor_atomic_update()
757 	value &= ~CURSOR_DST_BLEND_MASK;  in tegra_cursor_atomic_update()
758 	value &= ~CURSOR_SRC_BLEND_MASK;  in tegra_cursor_atomic_update()
759 	value |= CURSOR_MODE_NORMAL;  in tegra_cursor_atomic_update()
760 	value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;  in tegra_cursor_atomic_update()
761 	value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;  in tegra_cursor_atomic_update()
762 	value |= CURSOR_ALPHA;  in tegra_cursor_atomic_update()
763 	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);  in tegra_cursor_atomic_update()
766 	value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);  in tegra_cursor_atomic_update()
767 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);  in tegra_cursor_atomic_update()
774 	u32 value;  in tegra_cursor_atomic_disable()  local
782 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
783 	value &= ~CURSOR_ENABLE;  in tegra_cursor_atomic_disable()
784 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
929 	unsigned long value, flags;  in tegra_dc_enable_vblank()  local
933 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
934 	value |= VBLANK_INT;  in tegra_dc_enable_vblank()
935 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
942 	unsigned long value, flags;  in tegra_dc_disable_vblank()  local
946 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
947 	value &= ~VBLANK_INT;  in tegra_dc_disable_vblank()
948 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
1069 	unsigned long value;  in tegra_dc_set_timings()  local
1073 	value = (v_ref_to_sync << 16) | h_ref_to_sync;  in tegra_dc_set_timings()
1074 	tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);  in tegra_dc_set_timings()
1076 	value = ((mode->vsync_end - mode->vsync_start) << 16) |  in tegra_dc_set_timings()
1078 	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);  in tegra_dc_set_timings()
1080 	value = ((mode->vtotal - mode->vsync_end) << 16) |  in tegra_dc_set_timings()
1082 	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);  in tegra_dc_set_timings()
1084 	value = ((mode->vsync_start - mode->vdisplay) << 16) |  in tegra_dc_set_timings()
1086 	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);  in tegra_dc_set_timings()
1088 	value = (mode->vdisplay << 16) | mode->hdisplay;  in tegra_dc_set_timings()
1089 	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);  in tegra_dc_set_timings()
1126 	u32 value;  in tegra_dc_commit_state()  local
1153 	value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;  in tegra_dc_commit_state()
1154 	tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);  in tegra_dc_commit_state()
1159 	u32 value;  in tegra_dc_stop()  local
1162 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
1163 	value &= ~DISP_CTRL_MODE_MASK;  in tegra_dc_stop()
1164 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
1171 	u32 value;  in tegra_dc_idle()  local
1173 	value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_idle()
1175 	return (value & DISP_CTRL_MODE_MASK) == 0;  in tegra_dc_idle()
1196 	u32 value;  in tegra_crtc_disable()  local
1225 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_disable()
1226 		value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |  in tegra_crtc_disable()
1228 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_disable()
1240 	u32 value;  in tegra_crtc_enable()  local
1249 		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_enable()
1250 		value &= ~INTERLACE_ENABLE;  in tegra_crtc_enable()
1251 		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_enable()
1254 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_enable()
1255 	value &= ~DISP_CTRL_MODE_MASK;  in tegra_crtc_enable()
1256 	value |= DISP_CTRL_MODE_C_DISPLAY;  in tegra_crtc_enable()
1257 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_enable()
1259 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_enable()
1260 	value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |  in tegra_crtc_enable()
1262 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_enable()
1591 	u32 value;  in tegra_dc_show_crc()  local
1600 	value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;  in tegra_dc_show_crc()
1601 	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);  in tegra_dc_show_crc()
1607 	value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);  in tegra_dc_show_crc()
1608 	seq_printf(s, "%08x\n", value);  in tegra_dc_show_crc()
1702 	u32 value;  in tegra_dc_init()  local
1777 		value = SYNCPT_CNTRL_NO_STALL;  in tegra_dc_init()
1778 		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);  in tegra_dc_init()
1780 		value = SYNCPT_VSYNC_ENABLE | syncpt;  in tegra_dc_init()
1781 		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);  in tegra_dc_init()
1784 	value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |  in tegra_dc_init()
1786 	tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_dc_init()
1788 	value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |  in tegra_dc_init()
1790 	tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_dc_init()
1793 	value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |  in tegra_dc_init()
1795 	tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);  in tegra_dc_init()
1797 	value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |  in tegra_dc_init()
1799 	tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);  in tegra_dc_init()
1801 	value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |  in tegra_dc_init()
1803 	tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_dc_init()
1805 	value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |  in tegra_dc_init()
1807 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_init()
1935 	u32 value = 0;  in tegra_dc_parse_dt()  local
1938 	err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);  in tegra_dc_parse_dt()
1958 			value++;  in tegra_dc_parse_dt()
1962 	dc->pipe = value;  in tegra_dc_parse_dt()