Lines Matching refs:drm

633 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,  in tegra_dc_primary_plane_create()  argument
648 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc; in tegra_dc_primary_plane_create()
661 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_primary_plane_create()
804 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, in tegra_dc_cursor_plane_create() argument
828 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, in tegra_dc_cursor_plane_create()
873 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, in tegra_dc_overlay_plane_create() argument
891 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, in tegra_dc_overlay_plane_create()
904 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) in tegra_dc_add_planes() argument
910 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); in tegra_dc_add_planes()
955 struct drm_device *drm = dc->base.dev; in tegra_dc_finish_page_flip() local
960 spin_lock_irqsave(&drm->event_lock, flags); in tegra_dc_finish_page_flip()
963 spin_unlock_irqrestore(&drm->event_lock, flags); in tegra_dc_finish_page_flip()
985 spin_unlock_irqrestore(&drm->event_lock, flags); in tegra_dc_finish_page_flip()
991 struct drm_device *drm = crtc->dev; in tegra_dc_cancel_page_flip() local
994 spin_lock_irqsave(&drm->event_lock, flags); in tegra_dc_cancel_page_flip()
1002 spin_unlock_irqrestore(&drm->event_lock, flags); in tegra_dc_cancel_page_flip()
1696 struct drm_device *drm = dev_get_drvdata(client->parent); in tegra_dc_init() local
1699 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_init()
1720 primary = tegra_dc_primary_plane_create(drm, dc); in tegra_dc_init()
1727 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
1734 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
1749 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
1755 err = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
1760 err = tegra_dc_debugfs_init(dc, drm->primary); in tegra_dc_init()