Lines Matching refs:dc
92 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
97 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_readl_active()
99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
100 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
103 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_readl_active()
119 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
240 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, in tegra_dc_setup_window() argument
257 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_setup_window()
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_setup_window()
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
266 tegra_dc_writel(dc, value, DC_WIN_POSITION); in tegra_dc_setup_window()
269 tegra_dc_writel(dc, value, DC_WIN_SIZE); in tegra_dc_setup_window()
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); in tegra_dc_setup_window()
290 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); in tegra_dc_setup_window()
295 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); in tegra_dc_setup_window()
296 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); in tegra_dc_setup_window()
298 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); in tegra_dc_setup_window()
299 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); in tegra_dc_setup_window()
301 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
304 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
305 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
307 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
309 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
315 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); in tegra_dc_setup_window()
316 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); in tegra_dc_setup_window()
318 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
336 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND); in tegra_dc_setup_window()
357 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); in tegra_dc_setup_window()
364 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); in tegra_dc_setup_window()
365 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); in tegra_dc_setup_window()
366 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); in tegra_dc_setup_window()
367 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); in tegra_dc_setup_window()
368 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); in tegra_dc_setup_window()
369 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); in tegra_dc_setup_window()
370 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); in tegra_dc_setup_window()
371 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); in tegra_dc_setup_window()
381 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_dc_setup_window()
387 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); in tegra_dc_setup_window()
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); in tegra_dc_setup_window()
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
399 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
404 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
410 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_setup_window()
517 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_atomic_check() local
534 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
562 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_plane_atomic_update() local
596 tegra_dc_setup_window(dc, p->index, &window); in tegra_plane_atomic_update()
603 struct tegra_dc *dc; in tegra_plane_atomic_disable() local
611 dc = to_tegra_dc(old_state->crtc); in tegra_plane_atomic_disable()
613 spin_lock_irqsave(&dc->lock, flags); in tegra_plane_atomic_disable()
616 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_plane_atomic_disable()
618 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); in tegra_plane_atomic_disable()
620 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_plane_atomic_disable()
622 spin_unlock_irqrestore(&dc->lock, flags); in tegra_plane_atomic_disable()
634 struct tegra_dc *dc) in tegra_dc_primary_plane_create() argument
712 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_cursor_atomic_update() local
744 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
748 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
752 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
754 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
756 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
763 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
767 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
773 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
780 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
782 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
784 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
805 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
828 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, in tegra_dc_cursor_plane_create()
874 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
891 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, in tegra_dc_overlay_plane_create()
904 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) in tegra_dc_add_planes() argument
910 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i); in tegra_dc_add_planes()
918 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc) in tegra_dc_get_vblank_counter() argument
920 if (dc->syncpt) in tegra_dc_get_vblank_counter()
921 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
924 return drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
927 void tegra_dc_enable_vblank(struct tegra_dc *dc) in tegra_dc_enable_vblank() argument
931 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_enable_vblank()
933 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
935 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
937 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_enable_vblank()
940 void tegra_dc_disable_vblank(struct tegra_dc *dc) in tegra_dc_disable_vblank() argument
944 spin_lock_irqsave(&dc->lock, flags); in tegra_dc_disable_vblank()
946 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
948 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
950 spin_unlock_irqrestore(&dc->lock, flags); in tegra_dc_disable_vblank()
953 static void tegra_dc_finish_page_flip(struct tegra_dc *dc) in tegra_dc_finish_page_flip() argument
955 struct drm_device *drm = dc->base.dev; in tegra_dc_finish_page_flip()
956 struct drm_crtc *crtc = &dc->base; in tegra_dc_finish_page_flip()
962 if (!dc->event) { in tegra_dc_finish_page_flip()
969 spin_lock(&dc->lock); in tegra_dc_finish_page_flip()
972 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_finish_page_flip()
973 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
974 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); in tegra_dc_finish_page_flip()
975 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
977 spin_unlock(&dc->lock); in tegra_dc_finish_page_flip()
980 drm_crtc_send_vblank_event(crtc, dc->event); in tegra_dc_finish_page_flip()
982 dc->event = NULL; in tegra_dc_finish_page_flip()
990 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_cancel_page_flip() local
996 if (dc->event && dc->event->base.file_priv == file) { in tegra_dc_cancel_page_flip()
997 dc->event->base.destroy(&dc->event->base); in tegra_dc_cancel_page_flip()
999 dc->event = NULL; in tegra_dc_cancel_page_flip()
1064 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1071 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1074 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1078 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1082 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1086 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1089 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1106 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1113 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1123 static void tegra_dc_commit_state(struct tegra_dc *dc, in tegra_dc_commit_state() argument
1129 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1131 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1144 dev_err(dc->dev, in tegra_dc_commit_state()
1149 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1154 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_dc_commit_state()
1157 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1162 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1164 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1166 tegra_dc_commit(dc); in tegra_dc_stop()
1169 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1173 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1178 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1183 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1189 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1195 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_disable() local
1198 if (!tegra_dc_idle(dc)) { in tegra_crtc_disable()
1199 tegra_dc_stop(dc); in tegra_crtc_disable()
1205 tegra_dc_wait_idle(dc, 100); in tegra_crtc_disable()
1224 if (dc->rgb) { in tegra_crtc_disable()
1225 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_disable()
1228 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_disable()
1231 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_disable()
1239 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_enable() local
1242 tegra_dc_commit_state(dc, state); in tegra_crtc_enable()
1245 tegra_dc_set_timings(dc, mode); in tegra_crtc_enable()
1248 if (dc->soc->supports_interlacing) { in tegra_crtc_enable()
1249 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_enable()
1251 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_enable()
1254 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_enable()
1257 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_enable()
1259 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_enable()
1262 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_enable()
1264 tegra_dc_commit(dc); in tegra_crtc_enable()
1278 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_begin() local
1285 dc->event = crtc->state->event; in tegra_crtc_atomic_begin()
1294 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
1296 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1297 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1310 struct tegra_dc *dc = data; in tegra_dc_irq() local
1313 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
1314 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
1320 dc->stats.frames++; in tegra_dc_irq()
1327 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
1328 tegra_dc_finish_page_flip(dc); in tegra_dc_irq()
1329 dc->stats.vblank++; in tegra_dc_irq()
1336 dc->stats.underflow++; in tegra_dc_irq()
1343 dc->stats.overflow++; in tegra_dc_irq()
1352 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1355 drm_modeset_lock_crtc(&dc->base, NULL); in tegra_dc_show_regs()
1357 if (!dc->base.state->active) { in tegra_dc_show_regs()
1364 tegra_dc_readl(dc, name)) in tegra_dc_show_regs()
1582 drm_modeset_unlock_crtc(&dc->base); in tegra_dc_show_regs()
1589 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1593 drm_modeset_lock_crtc(&dc->base, NULL); in tegra_dc_show_crc()
1595 if (!dc->base.state->active) { in tegra_dc_show_crc()
1601 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1602 tegra_dc_commit(dc); in tegra_dc_show_crc()
1604 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1605 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1607 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1610 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1613 drm_modeset_unlock_crtc(&dc->base); in tegra_dc_show_crc()
1620 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1622 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1623 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1624 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1625 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1636 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) in tegra_dc_debugfs_init() argument
1642 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); in tegra_dc_debugfs_init()
1643 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); in tegra_dc_debugfs_init()
1646 if (!dc->debugfs) in tegra_dc_debugfs_init()
1649 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_debugfs_init()
1651 if (!dc->debugfs_files) { in tegra_dc_debugfs_init()
1657 dc->debugfs_files[i].data = dc; in tegra_dc_debugfs_init()
1659 err = drm_debugfs_create_files(dc->debugfs_files, in tegra_dc_debugfs_init()
1661 dc->debugfs, minor); in tegra_dc_debugfs_init()
1665 dc->minor = minor; in tegra_dc_debugfs_init()
1670 kfree(dc->debugfs_files); in tegra_dc_debugfs_init()
1671 dc->debugfs_files = NULL; in tegra_dc_debugfs_init()
1673 debugfs_remove(dc->debugfs); in tegra_dc_debugfs_init()
1674 dc->debugfs = NULL; in tegra_dc_debugfs_init()
1679 static int tegra_dc_debugfs_exit(struct tegra_dc *dc) in tegra_dc_debugfs_exit() argument
1681 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), in tegra_dc_debugfs_exit()
1682 dc->minor); in tegra_dc_debugfs_exit()
1683 dc->minor = NULL; in tegra_dc_debugfs_exit()
1685 kfree(dc->debugfs_files); in tegra_dc_debugfs_exit()
1686 dc->debugfs_files = NULL; in tegra_dc_debugfs_exit()
1688 debugfs_remove(dc->debugfs); in tegra_dc_debugfs_exit()
1689 dc->debugfs = NULL; in tegra_dc_debugfs_exit()
1698 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
1705 dc->syncpt = host1x_syncpt_request(dc->dev, flags); in tegra_dc_init()
1706 if (!dc->syncpt) in tegra_dc_init()
1707 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
1710 err = iommu_attach_device(tegra->domain, dc->dev); in tegra_dc_init()
1712 dev_err(dc->dev, "failed to attach to domain: %d\n", in tegra_dc_init()
1717 dc->domain = tegra->domain; in tegra_dc_init()
1720 primary = tegra_dc_primary_plane_create(drm, dc); in tegra_dc_init()
1726 if (dc->soc->supports_cursor) { in tegra_dc_init()
1727 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
1734 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
1739 drm_mode_crtc_set_gamma_size(&dc->base, 256); in tegra_dc_init()
1740 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
1746 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
1747 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
1749 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
1751 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
1755 err = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
1760 err = tegra_dc_debugfs_init(dc, drm->primary); in tegra_dc_init()
1762 dev_err(dc->dev, "debugfs setup failed: %d\n", err); in tegra_dc_init()
1765 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
1766 dev_name(dc->dev), dc); in tegra_dc_init()
1768 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
1774 if (dc->syncpt) { in tegra_dc_init()
1775 u32 syncpt = host1x_syncpt_id(dc->syncpt); in tegra_dc_init()
1778 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_dc_init()
1781 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_dc_init()
1786 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_dc_init()
1790 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_dc_init()
1795 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_dc_init()
1799 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_dc_init()
1803 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_dc_init()
1807 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_init()
1809 if (dc->soc->supports_border_color) in tegra_dc_init()
1810 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_dc_init()
1812 tegra_dc_stats_reset(&dc->stats); in tegra_dc_init()
1824 iommu_detach_device(tegra->domain, dc->dev); in tegra_dc_init()
1825 dc->domain = NULL; in tegra_dc_init()
1833 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
1836 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
1839 err = tegra_dc_debugfs_exit(dc); in tegra_dc_exit()
1841 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); in tegra_dc_exit()
1844 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
1846 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
1850 if (dc->domain) { in tegra_dc_exit()
1851 iommu_detach_device(dc->domain, dc->dev); in tegra_dc_exit()
1852 dc->domain = NULL; in tegra_dc_exit()
1855 host1x_syncpt_free(dc->syncpt); in tegra_dc_exit()
1932 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
1938 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
1940 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
1955 if (np == dc->dev->of_node) in tegra_dc_parse_dt()
1962 dc->pipe = value; in tegra_dc_parse_dt()
1971 struct tegra_dc *dc; in tegra_dc_probe() local
1974 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
1975 if (!dc) in tegra_dc_probe()
1982 spin_lock_init(&dc->lock); in tegra_dc_probe()
1983 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
1984 dc->dev = &pdev->dev; in tegra_dc_probe()
1985 dc->soc = id->data; in tegra_dc_probe()
1987 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
1991 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
1992 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
1994 return PTR_ERR(dc->clk); in tegra_dc_probe()
1997 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
1998 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
2000 return PTR_ERR(dc->rst); in tegra_dc_probe()
2003 if (dc->soc->has_powergate) { in tegra_dc_probe()
2004 if (dc->pipe == 0) in tegra_dc_probe()
2005 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
2007 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
2009 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_probe()
2010 dc->rst); in tegra_dc_probe()
2017 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
2024 err = reset_control_deassert(dc->rst); in tegra_dc_probe()
2033 dc->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dc_probe()
2034 if (IS_ERR(dc->regs)) in tegra_dc_probe()
2035 return PTR_ERR(dc->regs); in tegra_dc_probe()
2037 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
2038 if (dc->irq < 0) { in tegra_dc_probe()
2043 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
2044 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
2045 dc->client.dev = &pdev->dev; in tegra_dc_probe()
2047 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
2053 err = host1x_client_register(&dc->client); in tegra_dc_probe()
2060 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
2067 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
2070 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
2077 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()
2083 reset_control_assert(dc->rst); in tegra_dc_remove()
2085 if (dc->soc->has_powergate) in tegra_dc_remove()
2086 tegra_powergate_power_off(dc->powergate); in tegra_dc_remove()
2088 clk_disable_unprepare(dc->clk); in tegra_dc_remove()