144 	list[0].tv.bo = &vm->page_directory->tbo;  in radeon_vm_get_bos()
150 		if (!vm->page_tables[i].bo)  in radeon_vm_get_bos()
153 		list[idx].robj = vm->page_tables[i].bo;  in radeon_vm_get_bos()
156 		list[idx].tv.bo = &list[idx].robj->tbo;  in radeon_vm_get_bos()
294 				       struct radeon_bo *bo)  in radeon_vm_bo_find()  argument
298 	list_for_each_entry(bo_va, &bo->va, bo_list) {  in radeon_vm_bo_find()
321 				      struct radeon_bo *bo)  in radeon_vm_bo_add()  argument
330 	bo_va->bo = bo;  in radeon_vm_bo_add()
339 	list_add_tail(&bo_va->bo_list, &bo->va);  in radeon_vm_bo_add()
388 			      struct radeon_bo *bo)  in radeon_vm_clear_bo()  argument
395 	r = radeon_bo_reserve(bo, false);  in radeon_vm_clear_bo()
399 	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);  in radeon_vm_clear_bo()
403 	addr = radeon_bo_gpu_offset(bo);  in radeon_vm_clear_bo()
404 	entries = radeon_bo_size(bo) / 8;  in radeon_vm_clear_bo()
421 	radeon_bo_fence(bo, ib.fence, false);  in radeon_vm_clear_bo()
427 	radeon_bo_unreserve(bo);  in radeon_vm_clear_bo()
450 	uint64_t size = radeon_bo_size(bo_va->bo);  in radeon_vm_bo_set_addr()
487 				"(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo,  in radeon_vm_bo_set_addr()
488 				soffset, tmp->bo, tmp->it.start, tmp->it.last);  in radeon_vm_bo_set_addr()
507 		tmp->bo = radeon_bo_ref(bo_va->bo);  in radeon_vm_bo_set_addr()
537 	radeon_bo_unreserve(bo_va->bo);  in radeon_vm_bo_set_addr()
543 		if (vm->page_tables[pt_idx].bo)  in radeon_vm_bo_set_addr()
564 		if (vm->page_tables[pt_idx].bo) {  in radeon_vm_bo_set_addr()
573 		vm->page_tables[pt_idx].bo = pt;  in radeon_vm_bo_set_addr()
580 	radeon_bo_unreserve(bo_va->bo);  in radeon_vm_bo_set_addr()
667 		struct radeon_bo *bo = vm->page_tables[pt_idx].bo;  in radeon_vm_update_page_directory()  local
670 		if (bo == NULL)  in radeon_vm_update_page_directory()
673 		pt = radeon_bo_gpu_offset(bo);  in radeon_vm_update_page_directory()
826 		struct radeon_bo *pt = vm->page_tables[pt_idx].bo;  in radeon_vm_update_ptes()
894 		radeon_bo_fence(vm->page_tables[i].bo, fence, true);  in radeon_vm_fence_pts()
923 			bo_va->bo, vm);  in radeon_vm_bo_update()
943 	if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm))  in radeon_vm_bo_update()
953 			if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))  in radeon_vm_bo_update()
1059 		radeon_bo_unref(&bo_va->bo);  in radeon_vm_clear_freed()
1131 		bo_va->bo = radeon_bo_ref(bo_va->bo);  in radeon_vm_bo_rmv()
1152 			     struct radeon_bo *bo)  in radeon_vm_bo_invalidate()  argument
1156 	list_for_each_entry(bo_va, &bo->va, bo_list) {  in radeon_vm_bo_invalidate()
1239 		r = radeon_bo_reserve(bo_va->bo, false);  in radeon_vm_fini()
1242 			radeon_bo_unreserve(bo_va->bo);  in radeon_vm_fini()
1248 		radeon_bo_unref(&bo_va->bo);  in radeon_vm_fini()
1254 		radeon_bo_unref(&vm->page_tables[i].bo);  in radeon_vm_fini()