839 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)  in r100_ring_hdp_flush()  argument
841 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r100_ring_hdp_flush()
842 	radeon_ring_write(ring, rdev->config.r100.hdp_cntl |  in r100_ring_hdp_flush()
844 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r100_ring_hdp_flush()
845 	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);  in r100_ring_hdp_flush()
853 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in r100_fence_ring_emit()  local
857 	radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  in r100_fence_ring_emit()
858 	radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);  in r100_fence_ring_emit()
859 	radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));  in r100_fence_ring_emit()
860 	radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);  in r100_fence_ring_emit()
862 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r100_fence_ring_emit()
863 	radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);  in r100_fence_ring_emit()
864 	r100_ring_hdp_flush(rdev, ring);  in r100_fence_ring_emit()
866 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r100_fence_ring_emit()
867 	radeon_ring_write(ring, fence->seq);  in r100_fence_ring_emit()
868 	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));  in r100_fence_ring_emit()
869 	radeon_ring_write(ring, RADEON_SW_INT_FIRE);  in r100_fence_ring_emit()
873 			      struct radeon_ring *ring,  in r100_semaphore_ring_emit()  argument
888 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in r100_copy_blit()  local
907 	r = radeon_ring_lock(rdev, ring, ndw);  in r100_copy_blit()
921 		radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));  in r100_copy_blit()
922 		radeon_ring_write(ring,  in r100_copy_blit()
934 		radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));  in r100_copy_blit()
935 		radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));  in r100_copy_blit()
936 		radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));  in r100_copy_blit()
937 		radeon_ring_write(ring, 0);  in r100_copy_blit()
938 		radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));  in r100_copy_blit()
939 		radeon_ring_write(ring, num_gpu_pages);  in r100_copy_blit()
940 		radeon_ring_write(ring, num_gpu_pages);  in r100_copy_blit()
941 		radeon_ring_write(ring, cur_pages | (stride_pixels << 16));  in r100_copy_blit()
943 	radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));  in r100_copy_blit()
944 	radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);  in r100_copy_blit()
945 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r100_copy_blit()
946 	radeon_ring_write(ring,  in r100_copy_blit()
952 		radeon_ring_unlock_undo(rdev, ring);  in r100_copy_blit()
955 	radeon_ring_unlock_commit(rdev, ring, false);  in r100_copy_blit()
974 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)  in r100_ring_start()  argument
978 	r = radeon_ring_lock(rdev, ring, 2);  in r100_ring_start()
982 	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));  in r100_ring_start()
983 	radeon_ring_write(ring,  in r100_ring_start()
988 	radeon_ring_unlock_commit(rdev, ring, false);  in r100_ring_start()
1057 		      struct radeon_ring *ring)  in r100_gfx_get_rptr()  argument
1062 		rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);  in r100_gfx_get_rptr()
1070 		      struct radeon_ring *ring)  in r100_gfx_get_wptr()  argument
1080 		       struct radeon_ring *ring)  in r100_gfx_set_wptr()  argument
1082 	WREG32(RADEON_CP_RB_WPTR, ring->wptr);  in r100_gfx_set_wptr()
1111 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in r100_cp_init()  local
1137 	r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,  in r100_cp_init()
1147 	ring->align_mask = 16 - 1;  in r100_cp_init()
1177 	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);  in r100_cp_init()
1178 	WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);  in r100_cp_init()
1182 	ring->wptr = 0;  in r100_cp_init()
1183 	WREG32(RADEON_CP_RB_WPTR, ring->wptr);  in r100_cp_init()
1210 	radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);  in r100_cp_init()
1211 	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);  in r100_cp_init()
1216 	ring->ready = true;  in r100_cp_init()
1219 	if (!ring->rptr_save_reg /* not resuming from suspend */  in r100_cp_init()
1220 	    && radeon_ring_supports_scratch_reg(rdev, ring)) {  in r100_cp_init()
1221 		r = radeon_scratch_get(rdev, &ring->rptr_save_reg);  in r100_cp_init()
1224 			ring->rptr_save_reg = 0;  in r100_cp_init()
1237 	radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);  in r100_cp_fini()
1238 	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);  in r100_cp_fini()
1246 	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;  in r100_cp_disable()
2520 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)  in r100_gpu_is_lockup()  argument
2526 		radeon_ring_lockup_update(rdev, ring);  in r100_gpu_is_lockup()
2529 	return radeon_ring_test_lockup(rdev, ring);  in r100_gpu_is_lockup()
2951 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in r100_debugfs_cp_ring_info()  local
2955 	radeon_ring_free_size(rdev, ring);  in r100_debugfs_cp_ring_info()
2958 	count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;  in r100_debugfs_cp_ring_info()
2962 	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);  in r100_debugfs_cp_ring_info()
2964 	if (ring->ready) {  in r100_debugfs_cp_ring_info()
2966 			i = (rdp + j) & ring->ptr_mask;  in r100_debugfs_cp_ring_info()
2967 			seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);  in r100_debugfs_cp_ring_info()
3646 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)  in r100_ring_test()  argument
3659 	r = radeon_ring_lock(rdev, ring, 2);  in r100_ring_test()
3665 	radeon_ring_write(ring, PACKET0(scratch, 0));  in r100_ring_test()
3666 	radeon_ring_write(ring, 0xDEADBEEF);  in r100_ring_test()
3667 	radeon_ring_unlock_commit(rdev, ring, false);  in r100_ring_test()
3688 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in r100_ring_ib_execute()  local
3690 	if (ring->rptr_save_reg) {  in r100_ring_ib_execute()
3691 		u32 next_rptr = ring->wptr + 2 + 3;  in r100_ring_ib_execute()
3692 		radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));  in r100_ring_ib_execute()
3693 		radeon_ring_write(ring, next_rptr);  in r100_ring_ib_execute()
3696 	radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));  in r100_ring_ib_execute()
3697 	radeon_ring_write(ring, ib->gpu_addr);  in r100_ring_ib_execute()
3698 	radeon_ring_write(ring, ib->length_dw);  in r100_ring_ib_execute()
3701 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)  in r100_ib_test()  argument
3765 	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;  in r100_mc_stop()