660 	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);  in r100_pci_gart_enable()
661 	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);  in r100_pci_gart_enable()
668 		 (unsigned)(rdev->mc.gtt_size >> 20),  in r100_pci_gart_enable()
1217 	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);  in r100_cp_init()
1245 	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);  in r100_cp_disable()
2705 	rdev->mc.vram_is_ddr = false;  in r100_vram_get_type()
2707 		rdev->mc.vram_is_ddr = true;  in r100_vram_get_type()
2709 		rdev->mc.vram_is_ddr = true;  in r100_vram_get_type()
2715 			rdev->mc.vram_width = 32;  in r100_vram_get_type()
2717 			rdev->mc.vram_width = 64;  in r100_vram_get_type()
2720 			rdev->mc.vram_width /= 4;  in r100_vram_get_type()
2721 			rdev->mc.vram_is_ddr = true;  in r100_vram_get_type()
2726 			rdev->mc.vram_width = 128;  in r100_vram_get_type()
2728 			rdev->mc.vram_width = 64;  in r100_vram_get_type()
2732 		rdev->mc.vram_width = 128;  in r100_vram_get_type()
2779 	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);  in r100_vram_init_sizes()
2780 	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);  in r100_vram_init_sizes()
2781 	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);  in r100_vram_init_sizes()
2783 	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)  in r100_vram_init_sizes()
2784 		rdev->mc.visible_vram_size = rdev->mc.aper_size;  in r100_vram_init_sizes()
2790 		rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);  in r100_vram_init_sizes()
2791 		WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);  in r100_vram_init_sizes()
2792 		rdev->mc.mc_vram_size = rdev->mc.real_vram_size;  in r100_vram_init_sizes()
2794 		rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);  in r100_vram_init_sizes()
2798 		if (rdev->mc.real_vram_size == 0) {  in r100_vram_init_sizes()
2799 			rdev->mc.real_vram_size = 8192 * 1024;  in r100_vram_init_sizes()
2800 			WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);  in r100_vram_init_sizes()
2805 		if (rdev->mc.aper_size > config_aper_size)  in r100_vram_init_sizes()
2806 			config_aper_size = rdev->mc.aper_size;  in r100_vram_init_sizes()
2808 		if (config_aper_size > rdev->mc.real_vram_size)  in r100_vram_init_sizes()
2809 			rdev->mc.mc_vram_size = config_aper_size;  in r100_vram_init_sizes()
2811 			rdev->mc.mc_vram_size = rdev->mc.real_vram_size;  in r100_vram_init_sizes()
2835 	base = rdev->mc.aper_base;  in r100_mc_init()
2838 	radeon_vram_location(rdev, &rdev->mc, base);  in r100_mc_init()
2839 	rdev->mc.gtt_base_align = 0;  in r100_mc_init()
2841 		radeon_gtt_location(rdev, &rdev->mc);  in r100_mc_init()
3259 	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);  in r100_bandwidth_update()
3391 			if (rdev->mc.vram_is_ddr)  in r100_bandwidth_update()
3396 			if (rdev->mc.vram_width == 128)  in r100_bandwidth_update()
3405 	if (rdev->mc.vram_is_ddr) {  in r100_bandwidth_update()
3406 		if (rdev->mc.vram_width == 32) {  in r100_bandwidth_update()
3433 	temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));  in r100_bandwidth_update()
3574 			temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;  in r100_bandwidth_update()
3805 	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);  in r100_mc_resume()
3807 		WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);  in r100_mc_resume()
3843 			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |  in r100_mc_program()
3844 			S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));  in r100_mc_program()
3845 		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));  in r100_mc_program()
3848 				upper_32_bits(rdev->mc.agp_base) & 0xff);  in r100_mc_program()
3860 		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |  in r100_mc_program()
3861 		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));  in r100_mc_program()