164 	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);  in r100_page_flip()
176 	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);  in r100_page_flip()
359 			WREG32(voltage->gpio.reg, tmp);  in r100_pm_misc()
368 			WREG32(voltage->gpio.reg, tmp);  in r100_pm_misc()
457 				WREG32(RADEON_CRTC2_GEN_CNTL, tmp);  in r100_pm_prepare()
461 				WREG32(RADEON_CRTC_GEN_CNTL, tmp);  in r100_pm_prepare()
488 				WREG32(RADEON_CRTC2_GEN_CNTL, tmp);  in r100_pm_finish()
492 				WREG32(RADEON_CRTC_GEN_CNTL, tmp);  in r100_pm_finish()
564 		WREG32(RADEON_FP_GEN_CNTL, tmp);  in r100_hpd_set_polarity()
572 		WREG32(RADEON_FP2_GEN_CNTL, tmp);  in r100_hpd_set_polarity()
658 	WREG32(RADEON_AIC_CNTL, tmp);  in r100_pci_gart_enable()
660 	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);  in r100_pci_gart_enable()
661 	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);  in r100_pci_gart_enable()
663 	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);  in r100_pci_gart_enable()
665 	WREG32(RADEON_AIC_CNTL, tmp);  in r100_pci_gart_enable()
680 	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);  in r100_pci_gart_disable()
681 	WREG32(RADEON_AIC_LO_ADDR, 0);  in r100_pci_gart_disable()
682 	WREG32(RADEON_AIC_HI_ADDR, 0);  in r100_pci_gart_disable()
710 		WREG32(R_000040_GEN_INT_CNTL, 0);  in r100_irq_set()
730 	WREG32(RADEON_GEN_INT_CNTL, tmp);  in r100_irq_set()
742 	WREG32(R_000040_GEN_INT_CNTL, 0);  in r100_irq_disable()
746 	WREG32(R_000044_GEN_INT_STATUS, tmp);  in r100_irq_disable()
757 		WREG32(RADEON_GEN_INT_STATUS, irqs);  in r100_irq_ack()
815 			WREG32(RADEON_AIC_CNTL, msi_rearm);  in r100_irq_process()
816 			WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);  in r100_irq_process()
819 			WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);  in r100_irq_process()
1082 	WREG32(RADEON_CP_RB_WPTR, ring->wptr);  in r100_gfx_set_wptr()
1099 		WREG32(RADEON_CP_ME_RAM_ADDR, 0);  in r100_cp_load_microcode()
1101 			WREG32(RADEON_CP_ME_RAM_DATAH,  in r100_cp_load_microcode()
1103 			WREG32(RADEON_CP_ME_RAM_DATAL,  in r100_cp_load_microcode()
1167 	WREG32(0x718, pre_write_timer | (pre_write_limit << 28));  in r100_cp_init()
1174 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);  in r100_cp_init()
1178 	WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);  in r100_cp_init()
1180 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);  in r100_cp_init()
1181 	WREG32(RADEON_CP_RB_RPTR_WR, 0);  in r100_cp_init()
1183 	WREG32(RADEON_CP_RB_WPTR, ring->wptr);  in r100_cp_init()
1186 	WREG32(R_00070C_CP_RB_RPTR_ADDR,  in r100_cp_init()
1188 	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);  in r100_cp_init()
1191 		WREG32(R_000770_SCRATCH_UMSK, 0xff);  in r100_cp_init()
1194 		WREG32(R_000770_SCRATCH_UMSK, 0);  in r100_cp_init()
1197 	WREG32(RADEON_CP_RB_CNTL, tmp);  in r100_cp_init()
1200 	WREG32(RADEON_CP_CSQ_MODE,  in r100_cp_init()
1203 	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);  in r100_cp_init()
1204 	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);  in r100_cp_init()
1205 	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);  in r100_cp_init()
1247 	WREG32(RADEON_CP_CSQ_MODE, 0);  in r100_cp_disable()
1248 	WREG32(RADEON_CP_CSQ_CNTL, 0);  in r100_cp_disable()
1249 	WREG32(R_000770_SCRATCH_UMSK, 0);  in r100_cp_disable()
2538 	WREG32(RADEON_BUS_CNTL, tmp);  in r100_enable_bm()
2547 	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);  in r100_bm_disable()
2549 	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);  in r100_bm_disable()
2551 	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);  in r100_bm_disable()
2572 	WREG32(RADEON_CP_CSQ_CNTL, 0);  in r100_asic_reset()
2574 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);  in r100_asic_reset()
2575 	WREG32(RADEON_CP_RB_RPTR_WR, 0);  in r100_asic_reset()
2576 	WREG32(RADEON_CP_RB_WPTR, 0);  in r100_asic_reset()
2577 	WREG32(RADEON_CP_RB_CNTL, tmp);  in r100_asic_reset()
2582 	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |  in r100_asic_reset()
2588 	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);  in r100_asic_reset()
2593 	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));  in r100_asic_reset()
2596 	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);  in r100_asic_reset()
2621 	WREG32(RADEON_OV0_SCALE_CNTL, 0);  in r100_set_common_regs()
2622 	WREG32(RADEON_SUBPIC_CNTL, 0);  in r100_set_common_regs()
2623 	WREG32(RADEON_VIPH_CONTROL, 0);  in r100_set_common_regs()
2624 	WREG32(RADEON_I2C_CNTL_1, 0);  in r100_set_common_regs()
2625 	WREG32(RADEON_DVI_I2C_CNTL_1, 0);  in r100_set_common_regs()
2626 	WREG32(RADEON_CAP0_TRIG_CNTL, 0);  in r100_set_common_regs()
2627 	WREG32(RADEON_CAP1_TRIG_CNTL, 0);  in r100_set_common_regs()
2686 		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);  in r100_set_common_regs()
2687 		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);  in r100_set_common_regs()
2688 		WREG32(RADEON_DAC_CNTL2, dac2_cntl);  in r100_set_common_regs()
2791 		WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);  in r100_vram_init_sizes()
2800 			WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);  in r100_vram_init_sizes()
2826 	WREG32(RADEON_CONFIG_CNTL, temp);  in r100_vga_set_state()
2876 		WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);  in r100_pll_errata_after_data()
2878 		WREG32(RADEON_CLOCK_CNTL_INDEX, save);  in r100_pll_errata_after_data()
2903 	WREG32(RADEON_CLOCK_CNTL_DATA, v);  in r100_pll_wreg()
2937 		WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);  in r100_debugfs_rbbm_info()
2939 		WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);  in r100_debugfs_rbbm_info()
3005 		WREG32(RADEON_CP_CSQ_ADDR, i << 2);  in r100_debugfs_cp_csq_fifo()
3011 		WREG32(RADEON_CP_CSQ_ADDR, i << 2);  in r100_debugfs_cp_csq_fifo()
3017 		WREG32(RADEON_CP_CSQ_ADDR, i << 2);  in r100_debugfs_cp_csq_fifo()
3137 	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);  in r100_set_surface_reg()
3138 	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);  in r100_set_surface_reg()
3139 	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);  in r100_set_surface_reg()
3146 	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);  in r100_clear_surface_reg()
3250 		WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);  in r100_bandwidth_update()
3356 				WREG32(R300_MC_IND_INDEX, temp);  in r100_bandwidth_update()
3516 		WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |  in r100_bandwidth_update()
3526 			WREG32(RS400_DISP1_REQ_CNTL1, (temp |  in r100_bandwidth_update()
3532 			WREG32(RS400_DMIF_MEM_CNTL1, (temp |  in r100_bandwidth_update()
3608 		WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |  in r100_bandwidth_update()
3618 			WREG32(RS400_DISP2_REQ_CNTL1, (temp |  in r100_bandwidth_update()
3624 			WREG32(RS400_DISP2_REQ_CNTL2, (temp |  in r100_bandwidth_update()
3628 			WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);  in r100_bandwidth_update()
3629 			WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);  in r100_bandwidth_update()
3630 			WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);  in r100_bandwidth_update()
3631 			WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);  in r100_bandwidth_update()
3658 	WREG32(scratch, 0xCAFEDEAD);  in r100_ring_test()
3714 	WREG32(scratch, 0xCAFEDEAD);  in r100_ib_test()
3766 	WREG32(R_000740_CP_CSQ_CNTL, 0);  in r100_mc_stop()
3781 	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));  in r100_mc_stop()
3782 	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |  in r100_mc_stop()
3784 	WREG32(R_000050_CRTC_GEN_CNTL,  in r100_mc_stop()
3787 	WREG32(R_000420_OV0_SCALE_CNTL,  in r100_mc_stop()
3789 	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);  in r100_mc_stop()
3791 		WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |  in r100_mc_stop()
3793 		WREG32(R_0003F8_CRTC2_GEN_CNTL,  in r100_mc_stop()
3797 		WREG32(R_000360_CUR2_OFFSET,  in r100_mc_stop()
3805 	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);  in r100_mc_resume()
3807 		WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);  in r100_mc_resume()
3811 	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);  in r100_mc_resume()
3812 	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);  in r100_mc_resume()
3814 		WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);  in r100_mc_resume()
3842 		WREG32(R_00014C_MC_AGP_LOCATION,  in r100_mc_program()
3845 		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));  in r100_mc_program()
3847 			WREG32(R_00015C_AGP_BASE_2,  in r100_mc_program()
3850 		WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);  in r100_mc_program()
3851 		WREG32(R_000170_AGP_BASE, 0);  in r100_mc_program()
3853 			WREG32(R_00015C_AGP_BASE_2, 0);  in r100_mc_program()
3859 	WREG32(R_000148_MC_FB_LOCATION,  in r100_mc_program()
4006 		WREG32(RADEON_CP_CSQ_CNTL, 0);  in r100_restore_sanity()
4010 		WREG32(RADEON_CP_RB_CNTL, 0);  in r100_restore_sanity()
4014 		WREG32(RADEON_SCRATCH_UMSK, 0);  in r100_restore_sanity()