34 	struct nvkm_device *device = clk->base.subdev.device;  in read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base)  in read_pll_src()  argument
54 	struct nvkm_subdev *subdev = &clk->base.subdev;  in read_pll_src()
56 	u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_src()
63 		switch (base) {  in read_pll_src()
69 			nvkm_error(subdev, "ref: bad pll %06x\n", base);  in read_pll_src()
91 		switch (base) {  in read_pll_src()
97 			nvkm_error(subdev, "ref: bad pll %06x\n", base);  in read_pll_src()
103 		case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_src()
104 		case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in read_pll_src()
125 read_pll_ref(struct nv50_clk *clk, u32 base)  in read_pll_ref()  argument
127 	struct nvkm_subdev *subdev = &clk->base.subdev;  in read_pll_ref()
131 	switch (base) {  in read_pll_ref()
145 		return nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_ref()
147 		nvkm_error(subdev, "bad pll %06x\n", base);  in read_pll_ref()
152 		return nvkm_clk_read(&clk->base, nv_clk_src_href);  in read_pll_ref()
154 	return read_pll_src(clk, base);  in read_pll_ref()
158 read_pll(struct nv50_clk *clk, u32 base)  in read_pll()  argument
160 	struct nvkm_device *device = clk->base.subdev.device;  in read_pll()
162 	u32 ctrl = nvkm_rd32(device, base + 0);  in read_pll()
163 	u32 coef = nvkm_rd32(device, base + 4);  in read_pll()
164 	u32 ref = read_pll_ref(clk, base);  in read_pll()
168 	if (base == 0x004028 && (mast & 0x00100000)) {  in read_pll()
171 			return nvkm_clk_read(&clk->base, nv_clk_src_dom6);  in read_pll()
192 nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src)  in nv50_clk_read()  argument
194 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_read()
195 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv50_clk_read()
206 		return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000);  in nv50_clk_read()
208 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;  in nv50_clk_read()
210 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2;  in nv50_clk_read()
213 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in nv50_clk_read()
216 		case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);  in nv50_clk_read()
223 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
224 		case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);  in nv50_clk_read()
234 				return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P;  in nv50_clk_read()
235 			return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
246 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
249 				return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;  in nv50_clk_read()
267 					return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
268 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
276 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
282 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
286 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P;  in nv50_clk_read()
288 				return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P;  in nv50_clk_read()
306 			case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in nv50_clk_read()
308 			case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);  in nv50_clk_read()
310 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P;  in nv50_clk_read()
327 	struct nvkm_subdev *subdev = &clk->base.subdev;  in calc_pll()
368 nv50_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)  in nv50_clk_calc()  argument
370 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_calc()
372 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv50_clk_calc()
405 			out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2);  in nv50_clk_calc()
426 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) {  in nv50_clk_calc()
429 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) {  in nv50_clk_calc()
432 			freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;  in nv50_clk_calc()
495 nv50_clk_prog(struct nvkm_clk *base)  in nv50_clk_prog()  argument
497 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_prog()
502 nv50_clk_tidy(struct nvkm_clk *base)  in nv50_clk_tidy()  argument
504 	struct nv50_clk *clk = nv50_clk(base);  in nv50_clk_tidy()
517 	ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base);  in nv50_clk_new_()
518 	*pclk = &clk->base;  in nv50_clk_new_()