63 	struct nvkm_device *device = fifo->base.engine.subdev.device;  in nv40_fifo_init()  local
64 	struct nvkm_fb *fb = device->fb;  in nv40_fifo_init()
65 	struct nvkm_instmem *imem = device->imem;  in nv40_fifo_init()
70 	nvkm_wr32(device, 0x002040, 0x000000ff);  in nv40_fifo_init()
71 	nvkm_wr32(device, 0x002044, 0x2101ffff);  in nv40_fifo_init()
72 	nvkm_wr32(device, 0x002058, 0x00000001);  in nv40_fifo_init()
74 	nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |  in nv40_fifo_init()
77 	nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);  in nv40_fifo_init()
79 	switch (device->chipset) {  in nv40_fifo_init()
83 		nvkm_wr32(device, 0x002230, 0x00000001);  in nv40_fifo_init()
90 		nvkm_wr32(device, 0x002220, 0x00030002);  in nv40_fifo_init()
93 		nvkm_wr32(device, 0x002230, 0x00000000);  in nv40_fifo_init()
94 		nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +  in nv40_fifo_init()
100 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1);  in nv40_fifo_init()
102 	nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);  in nv40_fifo_init()
103 	nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);  in nv40_fifo_init()
105 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);  in nv40_fifo_init()
106 	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv40_fifo_init()
107 	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);  in nv40_fifo_init()
123 nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)  in nv40_fifo_new()  argument
125 	return nv04_fifo_new_(&nv40_fifo, device, index, 32,  in nv40_fifo_new()