Lines Matching refs:wm
289 dev_priv->wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
556 const struct intel_watermark_params *wm, in intel_calculate_wm() argument
571 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); in intel_calculate_wm()
575 wm_size = fifo_size - (entries_required + wm->guard_size); in intel_calculate_wm()
580 if (wm_size > (long)wm->max_wm) in intel_calculate_wm()
581 wm_size = wm->max_wm; in intel_calculate_wm()
583 wm_size = wm->default_wm; in intel_calculate_wm()
620 unsigned long wm; in pineview_update_wm() local
637 wm = intel_calculate_wm(clock, &pineview_display_wm, in pineview_update_wm()
642 reg |= FW_WM(wm, SR); in pineview_update_wm()
647 wm = intel_calculate_wm(clock, &pineview_cursor_wm, in pineview_update_wm()
652 reg |= FW_WM(wm, CURSOR_SR); in pineview_update_wm()
656 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, in pineview_update_wm()
661 reg |= FW_WM(wm, HPLL_SR); in pineview_update_wm()
665 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, in pineview_update_wm()
670 reg |= FW_WM(wm, HPLL_CURSOR); in pineview_update_wm()
820 const struct vlv_wm_values *wm) in vlv_write_wm_values() argument
826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | in vlv_write_wm_values()
827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | in vlv_write_wm_values()
828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | in vlv_write_wm_values()
829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); in vlv_write_wm_values()
832 FW_WM(wm->sr.plane, SR) | in vlv_write_wm_values()
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | in vlv_write_wm_values()
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | in vlv_write_wm_values()
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); in vlv_write_wm_values()
837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | in vlv_write_wm_values()
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | in vlv_write_wm_values()
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); in vlv_write_wm_values()
841 FW_WM(wm->sr.cursor, CURSOR_SR)); in vlv_write_wm_values()
845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | in vlv_write_wm_values()
849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); in vlv_write_wm_values()
851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | in vlv_write_wm_values()
852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); in vlv_write_wm_values()
854 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | in vlv_write_wm_values()
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | in vlv_write_wm_values()
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); in vlv_write_wm_values()
866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
869 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | in vlv_write_wm_values()
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); in vlv_write_wm_values()
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; in vlv_setup_wm_latency()
918 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; in vlv_setup_wm_latency()
921 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; in vlv_setup_wm_latency()
922 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; in vlv_setup_wm_latency()
924 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; in vlv_setup_wm_latency()
934 int clock, htotal, pixel_size, width, wm; in vlv_compute_wm_level() local
936 if (dev_priv->wm.pri_latency[level] == 0) in vlv_compute_wm_level()
956 wm = 63; in vlv_compute_wm_level()
958 wm = vlv_wm_method2(clock, htotal, width, pixel_size, in vlv_compute_wm_level()
959 dev_priv->wm.pri_latency[level] * 10); in vlv_compute_wm_level()
962 return min_t(int, wm, USHRT_MAX); in vlv_compute_wm_level()
993 plane->wm.fifo_size = 63; in vlv_compute_fifo()
998 plane->wm.fifo_size = 0; in vlv_compute_fifo()
1003 plane->wm.fifo_size = fifo_size * rate / total_rate; in vlv_compute_fifo()
1004 fifo_left -= plane->wm.fifo_size; in vlv_compute_fifo()
1020 if (plane->wm.fifo_size == 0 && in vlv_compute_fifo()
1025 plane->wm.fifo_size += plane_extra; in vlv_compute_fifo()
1049 wm_state->wm[level].cursor = plane->wm.fifo_size - in vlv_invert_wms()
1050 wm_state->wm[level].cursor; in vlv_invert_wms()
1053 wm_state->wm[level].primary = plane->wm.fifo_size - in vlv_invert_wms()
1054 wm_state->wm[level].primary; in vlv_invert_wms()
1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - in vlv_invert_wms()
1059 wm_state->wm[level].sprite[sprite]; in vlv_invert_wms()
1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; in vlv_compute_wm()
1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; in vlv_compute_wm()
1102 int wm = vlv_compute_wm_level(plane, crtc, state, level); in vlv_compute_wm() local
1106 if (WARN_ON(level == 0 && wm > max_wm)) in vlv_compute_wm()
1107 wm = max_wm; in vlv_compute_wm()
1109 if (wm > plane->wm.fifo_size) in vlv_compute_wm()
1115 wm_state->wm[level].cursor = wm; in vlv_compute_wm()
1118 wm_state->wm[level].primary = wm; in vlv_compute_wm()
1122 wm_state->wm[level].sprite[sprite] = wm; in vlv_compute_wm()
1138 wm_state->wm[level].cursor; in vlv_compute_wm()
1144 wm_state->wm[level].primary); in vlv_compute_wm()
1151 wm_state->wm[level].sprite[sprite]); in vlv_compute_wm()
1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { in vlv_compute_wm()
1158 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); in vlv_compute_wm()
1177 WARN_ON(plane->wm.fifo_size != 63); in vlv_pipe_set_fifo_size()
1182 sprite0_start = plane->wm.fifo_size; in vlv_pipe_set_fifo_size()
1184 sprite1_start = sprite0_start + plane->wm.fifo_size; in vlv_pipe_set_fifo_size()
1186 fifo_size = sprite1_start + plane->wm.fifo_size; in vlv_pipe_set_fifo_size()
1256 struct vlv_wm_values *wm) in vlv_merge_wm() argument
1261 wm->level = to_i915(dev)->wm.max_level; in vlv_merge_wm()
1262 wm->cxsr = true; in vlv_merge_wm()
1271 wm->cxsr = false; in vlv_merge_wm()
1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); in vlv_merge_wm()
1278 wm->cxsr = false; in vlv_merge_wm()
1281 wm->level = VLV_WM_LEVEL_PM2; in vlv_merge_wm()
1290 wm->pipe[pipe] = wm_state->wm[wm->level]; in vlv_merge_wm()
1291 if (wm->cxsr) in vlv_merge_wm()
1292 wm->sr = wm_state->sr[wm->level]; in vlv_merge_wm()
1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1307 struct vlv_wm_values wm = {}; in vlv_update_wm() local
1310 vlv_merge_wm(dev, &wm); in vlv_update_wm()
1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { in vlv_update_wm()
1318 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && in vlv_update_wm()
1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) in vlv_update_wm()
1322 if (wm.level < VLV_WM_LEVEL_PM5 && in vlv_update_wm()
1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) in vlv_update_wm()
1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) in vlv_update_wm()
1332 vlv_write_wm_values(intel_crtc, &wm); in vlv_update_wm()
1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, in vlv_update_wm()
1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], in vlv_update_wm()
1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); in vlv_update_wm()
1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) in vlv_update_wm()
1343 if (wm.level >= VLV_WM_LEVEL_PM5 && in vlv_update_wm()
1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) in vlv_update_wm()
1347 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && in vlv_update_wm()
1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) in vlv_update_wm()
1351 dev_priv->wm.vlv = wm; in vlv_update_wm()
1985 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; in ilk_compute_wm_level()
1986 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; in ilk_compute_wm_level()
1987 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; in ilk_compute_wm_level()
2045 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) in intel_read_wm_latency()
2067 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; in intel_read_wm_latency()
2068 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & in intel_read_wm_latency()
2070 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & in intel_read_wm_latency()
2072 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & in intel_read_wm_latency()
2087 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; in intel_read_wm_latency()
2088 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & in intel_read_wm_latency()
2090 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & in intel_read_wm_latency()
2092 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & in intel_read_wm_latency()
2112 wm[0] += 2; in intel_read_wm_latency()
2114 if (wm[level] != 0) in intel_read_wm_latency()
2115 wm[level] += 2; in intel_read_wm_latency()
2118 wm[i] = 0; in intel_read_wm_latency()
2125 wm[0] = (sskpd >> 56) & 0xFF; in intel_read_wm_latency()
2126 if (wm[0] == 0) in intel_read_wm_latency()
2127 wm[0] = sskpd & 0xF; in intel_read_wm_latency()
2128 wm[1] = (sskpd >> 4) & 0xFF; in intel_read_wm_latency()
2129 wm[2] = (sskpd >> 12) & 0xFF; in intel_read_wm_latency()
2130 wm[3] = (sskpd >> 20) & 0x1FF; in intel_read_wm_latency()
2131 wm[4] = (sskpd >> 32) & 0x1FF; in intel_read_wm_latency()
2135 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2136 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2137 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2138 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2143 wm[0] = 7; in intel_read_wm_latency()
2144 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; in intel_read_wm_latency()
2145 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; in intel_read_wm_latency()
2149 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) in intel_fixup_spr_wm_latency()
2153 wm[0] = 13; in intel_fixup_spr_wm_latency()
2156 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) in intel_fixup_cur_wm_latency()
2160 wm[0] = 13; in intel_fixup_cur_wm_latency()
2164 wm[3] *= 2; in intel_fixup_cur_wm_latency()
2182 const uint16_t wm[8]) in intel_print_wm_latency()
2187 unsigned int latency = wm[level]; in intel_print_wm_latency()
2205 name, level, wm[level], in intel_print_wm_latency()
2211 uint16_t wm[5], uint16_t min) in ilk_increase_wm_latency()
2215 if (wm[0] >= min) in ilk_increase_wm_latency()
2218 wm[0] = max(wm[0], min); in ilk_increase_wm_latency()
2220 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); in ilk_increase_wm_latency()
2234 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | in snb_wm_latency_quirk()
2235 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | in snb_wm_latency_quirk()
2236 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); in snb_wm_latency_quirk()
2242 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); in snb_wm_latency_quirk()
2243 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); in snb_wm_latency_quirk()
2244 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); in snb_wm_latency_quirk()
2251 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); in ilk_setup_wm_latency()
2253 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, in ilk_setup_wm_latency()
2254 sizeof(dev_priv->wm.pri_latency)); in ilk_setup_wm_latency()
2255 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, in ilk_setup_wm_latency()
2256 sizeof(dev_priv->wm.pri_latency)); in ilk_setup_wm_latency()
2258 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); in ilk_setup_wm_latency()
2259 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); in ilk_setup_wm_latency()
2261 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); in ilk_setup_wm_latency()
2262 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); in ilk_setup_wm_latency()
2263 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); in ilk_setup_wm_latency()
2273 intel_read_wm_latency(dev, dev_priv->wm.skl_latency); in skl_setup_wm_latency()
2274 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); in skl_setup_wm_latency()
2284 const struct intel_pipe_wm *wm = &intel_crtc->wm.active; in ilk_compute_wm_config() local
2286 if (!wm->pipe_enabled) in ilk_compute_wm_config()
2289 config->sprites_enabled |= wm->sprites_enabled; in ilk_compute_wm_config()
2290 config->sprites_scaled |= wm->sprites_scaled; in ilk_compute_wm_config()
2336 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); in intel_compute_pipe_wm()
2345 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) in intel_compute_pipe_wm()
2351 struct intel_wm_level wm = {}; in intel_compute_pipe_wm() local
2353 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); in intel_compute_pipe_wm()
2360 if (!ilk_validate_wm_level(level, &max, &wm)) in intel_compute_pipe_wm()
2363 pipe_wm->wm[level] = wm; in intel_compute_pipe_wm()
2381 const struct intel_pipe_wm *active = &intel_crtc->wm.active; in ilk_merge_wm_level()
2382 const struct intel_wm_level *wm = &active->wm[level]; in ilk_merge_wm_level() local
2392 if (!wm->enable) in ilk_merge_wm_level()
2395 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); in ilk_merge_wm_level()
2396 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); in ilk_merge_wm_level()
2397 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); in ilk_merge_wm_level()
2398 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); in ilk_merge_wm_level()
2424 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
2426 ilk_merge_wm_level(dev, level, wm); in ilk_wm_merge()
2429 wm->enable = false; in ilk_wm_merge()
2430 else if (!ilk_validate_wm_level(level, max, wm)) in ilk_wm_merge()
2438 if (wm->fbc_val > max->fbc) { in ilk_wm_merge()
2439 if (wm->enable) in ilk_wm_merge()
2441 wm->fbc_val = 0; in ilk_wm_merge()
2454 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
2456 wm->enable = false; in ilk_wm_merge()
2464 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); in ilk_wm_lp_to_level()
2475 return dev_priv->wm.pri_latency[level]; in ilk_wm_lp_latency()
2495 r = &merged->wm[level]; in ilk_compute_wm_results()
2531 &intel_crtc->wm.active.wm[0]; in ilk_compute_wm_results()
2536 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; in ilk_compute_wm_results()
2555 if (r1->wm[level].enable) in ilk_find_best_result()
2557 if (r2->wm[level].enable) in ilk_find_best_result()
2636 struct ilk_wm_values *previous = &dev_priv->wm.hw; in _ilk_disable_lp_wm()
2671 struct ilk_wm_values *previous = &dev_priv->wm.hw; in ilk_write_wm_values()
2740 dev_priv->wm.hw = *results; in ilk_write_wm_values()
3043 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; in skl_ddb_allocation_changed()
3070 config->sprites_enabled |= intel_plane->wm.enabled; in skl_compute_wm_global_parameters()
3071 config->sprites_scaled |= intel_plane->wm.scaled; in skl_compute_wm_global_parameters()
3130 p->plane[i++] = intel_plane->wm; in skl_compute_wm_pipe_parameters()
3142 uint32_t latency = dev_priv->wm.skl_latency[level]; in skl_compute_plane_wm()
3284 &pipe_wm->wm[level]); in skl_compute_pipe_wm()
3306 temp |= p_wm->wm[level].plane_res_l[i] << in skl_compute_wm_results()
3308 temp |= p_wm->wm[level].plane_res_b[i]; in skl_compute_wm_results()
3309 if (p_wm->wm[level].plane_en[i]) in skl_compute_wm_results()
3317 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; in skl_compute_wm_results()
3318 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; in skl_compute_wm_results()
3320 if (p_wm->wm[level].plane_en[PLANE_CURSOR]) in skl_compute_wm_results()
3463 cur_ddb = &dev_priv->wm.skl_hw.ddb; in skl_flush_wm_values()
3547 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) in skl_update_pipe_wm()
3550 intel_crtc->wm.skl_active = *pipe_wm; in skl_update_pipe_wm()
3630 struct skl_wm_values *results = &dev_priv->wm.skl_results; in skl_update_wm()
3654 dev_priv->wm.skl_hw = *results; in skl_update_wm()
3665 intel_plane->wm.enabled = enabled; in skl_update_sprite_wm()
3666 intel_plane->wm.scaled = scaled; in skl_update_sprite_wm()
3667 intel_plane->wm.horiz_pixels = sprite_width; in skl_update_sprite_wm()
3668 intel_plane->wm.vert_pixels = sprite_height; in skl_update_sprite_wm()
3669 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; in skl_update_sprite_wm()
3672 intel_plane->wm.bytes_per_pixel = in skl_update_sprite_wm()
3675 intel_plane->wm.y_bytes_per_pixel = in skl_update_sprite_wm()
3684 intel_plane->wm.tiling = fb->modifier[0]; in skl_update_sprite_wm()
3685 intel_plane->wm.rotation = plane->state->rotation; in skl_update_sprite_wm()
3707 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) in ilk_update_wm()
3710 intel_crtc->wm.active = pipe_wm; in ilk_update_wm()
3769 active->wm[level].plane_en[i] = is_enabled; in skl_pipe_wm_active_state()
3770 active->wm[level].plane_res_b[i] = in skl_pipe_wm_active_state()
3772 active->wm[level].plane_res_l[i] = in skl_pipe_wm_active_state()
3776 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; in skl_pipe_wm_active_state()
3777 active->wm[level].plane_res_b[PLANE_CURSOR] = in skl_pipe_wm_active_state()
3779 active->wm[level].plane_res_l[PLANE_CURSOR] = in skl_pipe_wm_active_state()
3806 struct skl_wm_values *hw = &dev_priv->wm.skl_hw; in skl_pipe_wm_get_hw_state()
3808 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; in skl_pipe_wm_get_hw_state()
3857 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; in skl_wm_get_hw_state()
3869 struct ilk_wm_values *hw = &dev_priv->wm.hw; in ilk_pipe_wm_get_hw_state()
3871 struct intel_pipe_wm *active = &intel_crtc->wm.active; in ilk_pipe_wm_get_hw_state()
3896 active->wm[0].enable = true; in ilk_pipe_wm_get_hw_state()
3897 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; in ilk_pipe_wm_get_hw_state()
3898 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; in ilk_pipe_wm_get_hw_state()
3899 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; in ilk_pipe_wm_get_hw_state()
3910 active->wm[level].enable = true; in ilk_pipe_wm_get_hw_state()
3920 struct vlv_wm_values *wm) in vlv_read_wm_values() argument
3928 wm->ddl[pipe].primary = in vlv_read_wm_values()
3930 wm->ddl[pipe].cursor = in vlv_read_wm_values()
3932 wm->ddl[pipe].sprite[0] = in vlv_read_wm_values()
3934 wm->ddl[pipe].sprite[1] = in vlv_read_wm_values()
3939 wm->sr.plane = _FW_WM(tmp, SR); in vlv_read_wm_values()
3940 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); in vlv_read_wm_values()
3941 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); in vlv_read_wm_values()
3942 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); in vlv_read_wm_values()
3945 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); in vlv_read_wm_values()
3946 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); in vlv_read_wm_values()
3947 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); in vlv_read_wm_values()
3950 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); in vlv_read_wm_values()
3954 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
3955 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
3958 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); in vlv_read_wm_values()
3959 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); in vlv_read_wm_values()
3962 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); in vlv_read_wm_values()
3963 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); in vlv_read_wm_values()
3966 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
3967 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; in vlv_read_wm_values()
3968 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; in vlv_read_wm_values()
3969 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; in vlv_read_wm_values()
3970 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
3971 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
3972 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
3973 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
3974 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
3975 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
3978 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
3979 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
3982 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
3983 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
3984 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
3985 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
3986 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
3987 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
3988 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
3998 struct vlv_wm_values *wm = &dev_priv->wm.vlv; in vlv_wm_get_hw_state() local
4003 vlv_read_wm_values(dev_priv, wm); in vlv_wm_get_hw_state()
4009 plane->wm.fifo_size = 63; in vlv_wm_get_hw_state()
4012 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); in vlv_wm_get_hw_state()
4016 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); in vlv_wm_get_hw_state()
4021 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in vlv_wm_get_hw_state()
4022 wm->level = VLV_WM_LEVEL_PM2; in vlv_wm_get_hw_state()
4029 wm->level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
4048 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
4052 wm->level = VLV_WM_LEVEL_DDR_DVFS; in vlv_wm_get_hw_state()
4060 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, in vlv_wm_get_hw_state()
4061 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); in vlv_wm_get_hw_state()
4064 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); in vlv_wm_get_hw_state()
4070 struct ilk_wm_values *hw = &dev_priv->wm.hw; in ilk_wm_get_hw_state()
7072 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && in intel_init_pm()
7073 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || in intel_init_pm()
7074 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && in intel_init_pm()
7075 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { in intel_init_pm()