Lines Matching refs:rps
244 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
259 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
266 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
275 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
2056 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2060 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2077 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2081 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
4025 mutex_lock(&dev_priv->rps.hw_lock); in vlv_wm_get_hw_state()
4055 mutex_unlock(&dev_priv->rps.hw_lock); in vlv_wm_get_hw_state()
4295 limits = (dev_priv->rps.max_freq_softlimit) << 23; in intel_rps_limits()
4296 if (val <= dev_priv->rps.min_freq_softlimit) in intel_rps_limits()
4297 limits |= (dev_priv->rps.min_freq_softlimit) << 14; in intel_rps_limits()
4299 limits = dev_priv->rps.max_freq_softlimit << 24; in intel_rps_limits()
4300 if (val <= dev_priv->rps.min_freq_softlimit) in intel_rps_limits()
4301 limits |= dev_priv->rps.min_freq_softlimit << 16; in intel_rps_limits()
4313 new_power = dev_priv->rps.power; in gen6_set_rps_thresholds()
4314 switch (dev_priv->rps.power) { in gen6_set_rps_thresholds()
4316 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4321 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4323 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4328 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4333 if (val <= dev_priv->rps.min_freq_softlimit) in gen6_set_rps_thresholds()
4335 if (val >= dev_priv->rps.max_freq_softlimit) in gen6_set_rps_thresholds()
4337 if (new_power == dev_priv->rps.power) in gen6_set_rps_thresholds()
4391 dev_priv->rps.power = new_power; in gen6_set_rps_thresholds()
4392 dev_priv->rps.up_threshold = threshold_up; in gen6_set_rps_thresholds()
4393 dev_priv->rps.down_threshold = threshold_down; in gen6_set_rps_thresholds()
4394 dev_priv->rps.last_adj = 0; in gen6_set_rps_thresholds()
4401 if (val > dev_priv->rps.min_freq_softlimit) in gen6_rps_pm_mask()
4403 if (val < dev_priv->rps.max_freq_softlimit) in gen6_rps_pm_mask()
4422 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in gen6_set_rps()
4423 WARN_ON(val > dev_priv->rps.max_freq); in gen6_set_rps()
4424 WARN_ON(val < dev_priv->rps.min_freq); in gen6_set_rps()
4429 if (val != dev_priv->rps.cur_freq) { in gen6_set_rps()
4453 dev_priv->rps.cur_freq = val; in gen6_set_rps()
4461 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in valleyview_set_rps()
4462 WARN_ON(val > dev_priv->rps.max_freq); in valleyview_set_rps()
4463 WARN_ON(val < dev_priv->rps.min_freq); in valleyview_set_rps()
4471 if (val != dev_priv->rps.cur_freq) { in valleyview_set_rps()
4477 dev_priv->rps.cur_freq = val; in valleyview_set_rps()
4490 u32 val = dev_priv->rps.idle_freq; in vlv_set_rps_idle()
4492 if (dev_priv->rps.cur_freq <= val) in vlv_set_rps_idle()
4504 mutex_lock(&dev_priv->rps.hw_lock); in gen6_rps_busy()
4505 if (dev_priv->rps.enabled) { in gen6_rps_busy()
4509 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); in gen6_rps_busy()
4511 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_rps_busy()
4518 mutex_lock(&dev_priv->rps.hw_lock); in gen6_rps_idle()
4519 if (dev_priv->rps.enabled) { in gen6_rps_idle()
4523 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen6_rps_idle()
4524 dev_priv->rps.last_adj = 0; in gen6_rps_idle()
4527 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_rps_idle()
4529 spin_lock(&dev_priv->rps.client_lock); in gen6_rps_idle()
4530 while (!list_empty(&dev_priv->rps.clients)) in gen6_rps_idle()
4531 list_del_init(dev_priv->rps.clients.next); in gen6_rps_idle()
4532 spin_unlock(&dev_priv->rps.client_lock); in gen6_rps_idle()
4536 struct intel_rps_client *rps, in gen6_rps_boost() argument
4543 dev_priv->rps.enabled && in gen6_rps_boost()
4544 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) in gen6_rps_boost()
4550 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) in gen6_rps_boost()
4551 rps = NULL; in gen6_rps_boost()
4553 spin_lock(&dev_priv->rps.client_lock); in gen6_rps_boost()
4554 if (rps == NULL || list_empty(&rps->link)) { in gen6_rps_boost()
4556 if (dev_priv->rps.interrupts_enabled) { in gen6_rps_boost()
4557 dev_priv->rps.client_boost = true; in gen6_rps_boost()
4558 queue_work(dev_priv->wq, &dev_priv->rps.work); in gen6_rps_boost()
4562 if (rps != NULL) { in gen6_rps_boost()
4563 list_add(&rps->link, &dev_priv->rps.clients); in gen6_rps_boost()
4564 rps->boosts++; in gen6_rps_boost()
4566 dev_priv->rps.boosts++; in gen6_rps_boost()
4568 spin_unlock(&dev_priv->rps.client_lock); in gen6_rps_boost()
4676 dev_priv->rps.cur_freq = 0; in gen6_init_rps_frequencies()
4680 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
4681 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
4682 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
4685 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
4686 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
4687 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
4691 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; in gen6_init_rps_frequencies()
4693 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; in gen6_init_rps_frequencies()
4699 dev_priv->rps.efficient_freq = in gen6_init_rps_frequencies()
4702 dev_priv->rps.min_freq, in gen6_init_rps_frequencies()
4703 dev_priv->rps.max_freq); in gen6_init_rps_frequencies()
4709 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4710 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4711 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4712 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4713 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4716 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
4719 if (dev_priv->rps.max_freq_softlimit == 0) in gen6_init_rps_frequencies()
4720 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in gen6_init_rps_frequencies()
4722 if (dev_priv->rps.min_freq_softlimit == 0) { in gen6_init_rps_frequencies()
4724 dev_priv->rps.min_freq_softlimit = in gen6_init_rps_frequencies()
4725 max_t(int, dev_priv->rps.efficient_freq, in gen6_init_rps_frequencies()
4728 dev_priv->rps.min_freq_softlimit = in gen6_init_rps_frequencies()
4729 dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
4750 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); in gen9_enable_rps()
4761 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen9_enable_rps()
4762 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); in gen9_enable_rps()
4886 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); in gen8_enable_rps()
4888 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); in gen8_enable_rps()
4894 dev_priv->rps.max_freq_softlimit << 24 | in gen8_enable_rps()
4895 dev_priv->rps.min_freq_softlimit << 16); in gen8_enable_rps()
4915 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen8_enable_rps()
4916 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen8_enable_rps()
4930 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in gen6_enable_rps()
5004 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, in gen6_enable_rps()
5006 dev_priv->rps.max_freq = pcu_mbox & 0xff; in gen6_enable_rps()
5009 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen6_enable_rps()
5010 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen6_enable_rps()
5039 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in __gen6_update_ring_freq()
5062 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; in __gen6_update_ring_freq()
5063 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; in __gen6_update_ring_freq()
5065 min_gpu_freq = dev_priv->rps.min_freq; in __gen6_update_ring_freq()
5066 max_gpu_freq = dev_priv->rps.max_freq; in __gen6_update_ring_freq()
5121 mutex_lock(&dev_priv->rps.hw_lock); in gen6_update_ring_freq()
5123 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_update_ring_freq()
5322 mutex_lock(&dev_priv->rps.hw_lock); in valleyview_init_gt_powersave()
5339 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); in valleyview_init_gt_powersave()
5340 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; in valleyview_init_gt_powersave()
5342 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), in valleyview_init_gt_powersave()
5343 dev_priv->rps.max_freq); in valleyview_init_gt_powersave()
5345 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); in valleyview_init_gt_powersave()
5347 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in valleyview_init_gt_powersave()
5348 dev_priv->rps.efficient_freq); in valleyview_init_gt_powersave()
5350 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); in valleyview_init_gt_powersave()
5352 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), in valleyview_init_gt_powersave()
5353 dev_priv->rps.rp1_freq); in valleyview_init_gt_powersave()
5355 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); in valleyview_init_gt_powersave()
5357 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in valleyview_init_gt_powersave()
5358 dev_priv->rps.min_freq); in valleyview_init_gt_powersave()
5360 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
5363 if (dev_priv->rps.max_freq_softlimit == 0) in valleyview_init_gt_powersave()
5364 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in valleyview_init_gt_powersave()
5366 if (dev_priv->rps.min_freq_softlimit == 0) in valleyview_init_gt_powersave()
5367 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
5369 mutex_unlock(&dev_priv->rps.hw_lock); in valleyview_init_gt_powersave()
5379 mutex_lock(&dev_priv->rps.hw_lock); in cherryview_init_gt_powersave()
5395 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); in cherryview_init_gt_powersave()
5396 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; in cherryview_init_gt_powersave()
5398 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), in cherryview_init_gt_powersave()
5399 dev_priv->rps.max_freq); in cherryview_init_gt_powersave()
5401 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); in cherryview_init_gt_powersave()
5403 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in cherryview_init_gt_powersave()
5404 dev_priv->rps.efficient_freq); in cherryview_init_gt_powersave()
5406 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); in cherryview_init_gt_powersave()
5408 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), in cherryview_init_gt_powersave()
5409 dev_priv->rps.rp1_freq); in cherryview_init_gt_powersave()
5412 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; in cherryview_init_gt_powersave()
5414 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in cherryview_init_gt_powersave()
5415 dev_priv->rps.min_freq); in cherryview_init_gt_powersave()
5417 WARN_ONCE((dev_priv->rps.max_freq | in cherryview_init_gt_powersave()
5418 dev_priv->rps.efficient_freq | in cherryview_init_gt_powersave()
5419 dev_priv->rps.rp1_freq | in cherryview_init_gt_powersave()
5420 dev_priv->rps.min_freq) & 1, in cherryview_init_gt_powersave()
5423 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
5426 if (dev_priv->rps.max_freq_softlimit == 0) in cherryview_init_gt_powersave()
5427 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in cherryview_init_gt_powersave()
5429 if (dev_priv->rps.min_freq_softlimit == 0) in cherryview_init_gt_powersave()
5430 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
5432 mutex_unlock(&dev_priv->rps.hw_lock); in cherryview_init_gt_powersave()
5447 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in cherryview_enable_rps()
5524 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in cherryview_enable_rps()
5526 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in cherryview_enable_rps()
5527 dev_priv->rps.cur_freq); in cherryview_enable_rps()
5530 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in cherryview_enable_rps()
5531 dev_priv->rps.efficient_freq); in cherryview_enable_rps()
5533 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); in cherryview_enable_rps()
5545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in valleyview_enable_rps()
5614 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in valleyview_enable_rps()
5616 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in valleyview_enable_rps()
5617 dev_priv->rps.cur_freq); in valleyview_enable_rps()
5620 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in valleyview_enable_rps()
5621 dev_priv->rps.efficient_freq); in valleyview_enable_rps()
5623 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); in valleyview_enable_rps()
5820 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); in __i915_gfx_val()
6138 flush_delayed_work(&dev_priv->rps.delayed_resume_work); in gen6_suspend_rps()
6173 mutex_lock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
6183 dev_priv->rps.enabled = false; in intel_disable_gt_powersave()
6184 mutex_unlock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
6192 rps.delayed_resume_work.work); in intel_gen6_powersave_work()
6195 mutex_lock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
6216 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()
6217 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); in intel_gen6_powersave_work()
6219 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()
6220 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); in intel_gen6_powersave_work()
6222 dev_priv->rps.enabled = true; in intel_gen6_powersave_work()
6226 mutex_unlock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
6257 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, in intel_enable_gt_powersave()
6271 dev_priv->rps.enabled = false; in intel_reset_gt_powersave()
7154 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in sandybridge_pcode_read()
7179 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in sandybridge_pcode_write()
7332 mutex_init(&dev_priv->rps.hw_lock); in intel_pm_setup()
7333 spin_lock_init(&dev_priv->rps.client_lock); in intel_pm_setup()
7335 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, in intel_pm_setup()
7337 INIT_LIST_HEAD(&dev_priv->rps.clients); in intel_pm_setup()
7338 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); in intel_pm_setup()
7339 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); in intel_pm_setup()