4164 	u16 rgvswctl;  in ironlake_set_drps()  local
4168 	rgvswctl = I915_READ16(MEMSWCTL);  in ironlake_set_drps()
4169 	if (rgvswctl & MEMCTL_CMD_STS) {  in ironlake_set_drps()
4174 	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |  in ironlake_set_drps()
4176 	I915_WRITE16(MEMSWCTL, rgvswctl);  in ironlake_set_drps()
4179 	rgvswctl |= MEMCTL_CMD_STS;  in ironlake_set_drps()
4180 	I915_WRITE16(MEMSWCTL, rgvswctl);  in ironlake_set_drps()
4256 	u16 rgvswctl;  in ironlake_disable_drps()  local
4260 	rgvswctl = I915_READ16(MEMSWCTL);  in ironlake_disable_drps()
4272 	rgvswctl |= MEMCTL_CMD_STS;  in ironlake_disable_drps()
4273 	I915_WRITE(MEMSWCTL, rgvswctl);  in ironlake_disable_drps()