Lines Matching refs:pipe
337 enum pipe pipe, int plane) in vlv_get_fifo_size() argument
342 switch (pipe) { in vlv_get_fifo_size()
381 pipe_name(pipe), plane == 0 ? "primary" : "sprite", in vlv_get_fifo_size()
382 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), in vlv_get_fifo_size()
823 enum pipe pipe = crtc->pipe; in vlv_write_wm_values() local
825 I915_WRITE(VLV_DDL(pipe), in vlv_write_wm_values()
826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | in vlv_write_wm_values()
827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | in vlv_write_wm_values()
828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | in vlv_write_wm_values()
829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); in vlv_write_wm_values()
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | in vlv_write_wm_values()
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | in vlv_write_wm_values()
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); in vlv_write_wm_values()
837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | in vlv_write_wm_values()
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | in vlv_write_wm_values()
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); in vlv_write_wm_values()
845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | in vlv_write_wm_values()
849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); in vlv_write_wm_values()
851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | in vlv_write_wm_values()
852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); in vlv_write_wm_values()
855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | in vlv_write_wm_values()
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | in vlv_write_wm_values()
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); in vlv_write_wm_values()
866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | in vlv_write_wm_values()
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); in vlv_write_wm_values()
1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; in vlv_compute_wm()
1192 pipe_name(crtc->pipe), sprite0_start, in vlv_pipe_set_fifo_size()
1195 switch (crtc->pipe) { in vlv_pipe_set_fifo_size()
1285 enum pipe pipe = crtc->pipe; in vlv_merge_wm() local
1290 wm->pipe[pipe] = wm_state->wm[wm->level]; in vlv_merge_wm()
1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
1306 enum pipe pipe = intel_crtc->pipe; in vlv_update_wm() local
1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, in vlv_update_wm()
1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], in vlv_update_wm()
2529 enum pipe pipe = intel_crtc->pipe; in ilk_compute_wm_results() local
2536 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; in ilk_compute_wm_results()
2538 results->wm_pipe[pipe] = in ilk_compute_wm_results()
2574 #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) argument
2575 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) argument
2586 enum pipe pipe; in ilk_compute_wm_dirty() local
2589 for_each_pipe(dev_priv, pipe) { in ilk_compute_wm_dirty()
2590 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { in ilk_compute_wm_dirty()
2591 dirty |= WM_DIRTY_LINETIME(pipe); in ilk_compute_wm_dirty()
2596 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { in ilk_compute_wm_dirty()
2597 dirty |= WM_DIRTY_PIPE(pipe); in ilk_compute_wm_dirty()
2817 enum pipe pipe; in skl_ddb_get_hw_state() local
2823 for_each_pipe(dev_priv, pipe) { in skl_ddb_get_hw_state()
2824 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) in skl_ddb_get_hw_state()
2827 for_each_plane(dev_priv, pipe, plane) { in skl_ddb_get_hw_state()
2828 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); in skl_ddb_get_hw_state()
2829 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], in skl_ddb_get_hw_state()
2833 val = I915_READ(CUR_BUF_CFG(pipe)); in skl_ddb_get_hw_state()
2834 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], in skl_ddb_get_hw_state()
2892 enum pipe pipe = intel_crtc->pipe; in skl_allocate_pipe_ddb() local
2893 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; in skl_allocate_pipe_ddb()
2903 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); in skl_allocate_pipe_ddb()
2904 memset(&ddb->plane[pipe][PLANE_CURSOR], 0, in skl_allocate_pipe_ddb()
2905 sizeof(ddb->plane[pipe][PLANE_CURSOR])); in skl_allocate_pipe_ddb()
2910 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; in skl_allocate_pipe_ddb()
2911 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; in skl_allocate_pipe_ddb()
2917 for_each_plane(dev_priv, pipe, plane) { in skl_allocate_pipe_ddb()
2959 ddb->plane[pipe][plane].start = start; in skl_allocate_pipe_ddb()
2960 ddb->plane[pipe][plane].end = start + plane_blocks; in skl_allocate_pipe_ddb()
2973 ddb->y_plane[pipe][plane].start = start; in skl_allocate_pipe_ddb()
2974 ddb->y_plane[pipe][plane].end = start + y_plane_blocks; in skl_allocate_pipe_ddb()
3044 enum pipe pipe = intel_crtc->pipe; in skl_ddb_allocation_changed() local
3046 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], in skl_ddb_allocation_changed()
3047 sizeof(new_ddb->plane[pipe]))) in skl_ddb_allocation_changed()
3050 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], in skl_ddb_allocation_changed()
3051 sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) in skl_ddb_allocation_changed()
3080 enum pipe pipe = intel_crtc->pipe; in skl_compute_wm_pipe_parameters() local
3128 if (intel_plane->pipe == pipe && in skl_compute_wm_pipe_parameters()
3216 enum pipe pipe, in skl_compute_wm_level() argument
3225 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); in skl_compute_wm_level()
3235 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); in skl_compute_wm_level()
3282 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, in skl_compute_pipe_wm()
3298 enum pipe pipe = intel_crtc->pipe; in skl_compute_wm_results() local
3312 r->plane[pipe][i][level] = temp; in skl_compute_wm_results()
3323 r->plane[pipe][PLANE_CURSOR][level] = temp; in skl_compute_wm_results()
3335 r->plane_trans[pipe][i] = temp; in skl_compute_wm_results()
3344 r->plane_trans[pipe][PLANE_CURSOR] = temp; in skl_compute_wm_results()
3346 r->wm_linetime[pipe] = p_wm->linetime; in skl_compute_wm_results()
3366 enum pipe pipe = crtc->pipe; in skl_write_wm_values() local
3368 if (!new->dirty[pipe]) in skl_write_wm_values()
3371 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); in skl_write_wm_values()
3375 I915_WRITE(PLANE_WM(pipe, i, level), in skl_write_wm_values()
3376 new->plane[pipe][i][level]); in skl_write_wm_values()
3377 I915_WRITE(CUR_WM(pipe, level), in skl_write_wm_values()
3378 new->plane[pipe][PLANE_CURSOR][level]); in skl_write_wm_values()
3381 I915_WRITE(PLANE_WM_TRANS(pipe, i), in skl_write_wm_values()
3382 new->plane_trans[pipe][i]); in skl_write_wm_values()
3383 I915_WRITE(CUR_WM_TRANS(pipe), in skl_write_wm_values()
3384 new->plane_trans[pipe][PLANE_CURSOR]); in skl_write_wm_values()
3388 PLANE_BUF_CFG(pipe, i), in skl_write_wm_values()
3389 &new->ddb.plane[pipe][i]); in skl_write_wm_values()
3391 PLANE_NV12_BUF_CFG(pipe, i), in skl_write_wm_values()
3392 &new->ddb.y_plane[pipe][i]); in skl_write_wm_values()
3395 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), in skl_write_wm_values()
3396 &new->ddb.plane[pipe][PLANE_CURSOR]); in skl_write_wm_values()
3425 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) in skl_wm_flush_pipe() argument
3429 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); in skl_wm_flush_pipe()
3431 for_each_plane(dev_priv, pipe, plane) { in skl_wm_flush_pipe()
3432 I915_WRITE(PLANE_SURF(pipe, plane), in skl_wm_flush_pipe()
3433 I915_READ(PLANE_SURF(pipe, plane))); in skl_wm_flush_pipe()
3435 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); in skl_wm_flush_pipe()
3441 enum pipe pipe) in skl_ddb_allocation_included() argument
3445 old_size = skl_ddb_entry_size(&old->pipe[pipe]); in skl_ddb_allocation_included()
3446 new_size = skl_ddb_entry_size(&new->pipe[pipe]); in skl_ddb_allocation_included()
3449 new->pipe[pipe].start >= old->pipe[pipe].start && in skl_ddb_allocation_included()
3450 new->pipe[pipe].end <= old->pipe[pipe].end; in skl_ddb_allocation_included()
3460 enum pipe pipe; in skl_flush_wm_values() local
3476 pipe = crtc->pipe; in skl_flush_wm_values()
3478 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) in skl_flush_wm_values()
3481 skl_wm_flush_pipe(dev_priv, pipe, 1); in skl_flush_wm_values()
3482 intel_wait_for_vblank(dev, pipe); in skl_flush_wm_values()
3484 reallocated[pipe] = true; in skl_flush_wm_values()
3499 pipe = crtc->pipe; in skl_flush_wm_values()
3501 if (reallocated[pipe]) in skl_flush_wm_values()
3504 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < in skl_flush_wm_values()
3505 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { in skl_flush_wm_values()
3506 skl_wm_flush_pipe(dev_priv, pipe, 2); in skl_flush_wm_values()
3507 intel_wait_for_vblank(dev, pipe); in skl_flush_wm_values()
3508 reallocated[pipe] = true; in skl_flush_wm_values()
3522 pipe = crtc->pipe; in skl_flush_wm_values()
3528 if (reallocated[pipe]) in skl_flush_wm_values()
3531 skl_wm_flush_pipe(dev_priv, pipe, 3); in skl_flush_wm_values()
3582 if (this_crtc->pipe == intel_crtc->pipe) in skl_update_other_pipe_wm()
3600 r->dirty[intel_crtc->pipe] = true; in skl_update_other_pipe_wm()
3604 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) in skl_clear_wm() argument
3606 watermarks->wm_linetime[pipe] = 0; in skl_clear_wm()
3607 memset(watermarks->plane[pipe], 0, in skl_clear_wm()
3609 memset(watermarks->plane_trans[pipe], in skl_clear_wm()
3611 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; in skl_clear_wm()
3614 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); in skl_clear_wm()
3615 memset(&watermarks->ddb.plane[pipe], 0, in skl_clear_wm()
3617 memset(&watermarks->ddb.y_plane[pipe], 0, in skl_clear_wm()
3619 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, in skl_clear_wm()
3638 skl_clear_wm(results, intel_crtc->pipe); in skl_update_wm()
3647 results->dirty[intel_crtc->pipe] = true; in skl_update_wm()
3753 intel_wait_for_vblank(dev, intel_plane->pipe); in ilk_update_sprite_wm()
3809 enum pipe pipe = intel_crtc->pipe; in skl_pipe_wm_get_hw_state() local
3815 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); in skl_pipe_wm_get_hw_state()
3819 hw->plane[pipe][i][level] = in skl_pipe_wm_get_hw_state()
3820 I915_READ(PLANE_WM(pipe, i, level)); in skl_pipe_wm_get_hw_state()
3821 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); in skl_pipe_wm_get_hw_state()
3825 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); in skl_pipe_wm_get_hw_state()
3826 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); in skl_pipe_wm_get_hw_state()
3831 hw->dirty[pipe] = true; in skl_pipe_wm_get_hw_state()
3833 active->linetime = hw->wm_linetime[pipe]; in skl_pipe_wm_get_hw_state()
3837 temp = hw->plane[pipe][i][level]; in skl_pipe_wm_get_hw_state()
3841 temp = hw->plane[pipe][PLANE_CURSOR][level]; in skl_pipe_wm_get_hw_state()
3846 temp = hw->plane_trans[pipe][i]; in skl_pipe_wm_get_hw_state()
3850 temp = hw->plane_trans[pipe][PLANE_CURSOR]; in skl_pipe_wm_get_hw_state()
3872 enum pipe pipe = intel_crtc->pipe; in ilk_pipe_wm_get_hw_state() local
3879 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); in ilk_pipe_wm_get_hw_state()
3881 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); in ilk_pipe_wm_get_hw_state()
3888 u32 tmp = hw->wm_pipe[pipe]; in ilk_pipe_wm_get_hw_state()
3900 active->linetime = hw->wm_linetime[pipe]; in ilk_pipe_wm_get_hw_state()
3922 enum pipe pipe; in vlv_read_wm_values() local
3925 for_each_pipe(dev_priv, pipe) { in vlv_read_wm_values()
3926 tmp = I915_READ(VLV_DDL(pipe)); in vlv_read_wm_values()
3928 wm->ddl[pipe].primary = in vlv_read_wm_values()
3930 wm->ddl[pipe].cursor = in vlv_read_wm_values()
3932 wm->ddl[pipe].sprite[0] = in vlv_read_wm_values()
3934 wm->ddl[pipe].sprite[1] = in vlv_read_wm_values()
3940 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); in vlv_read_wm_values()
3941 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); in vlv_read_wm_values()
3942 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); in vlv_read_wm_values()
3945 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); in vlv_read_wm_values()
3946 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); in vlv_read_wm_values()
3947 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); in vlv_read_wm_values()
3954 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
3955 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
3958 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); in vlv_read_wm_values()
3959 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); in vlv_read_wm_values()
3962 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); in vlv_read_wm_values()
3963 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); in vlv_read_wm_values()
3967 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; in vlv_read_wm_values()
3968 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; in vlv_read_wm_values()
3969 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; in vlv_read_wm_values()
3970 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
3971 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
3972 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
3973 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
3974 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
3975 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
3978 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
3979 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
3983 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
3984 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
3985 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
3986 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
3987 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
3988 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
4000 enum pipe pipe; in vlv_wm_get_hw_state() local
4012 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); in vlv_wm_get_hw_state()
4016 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); in vlv_wm_get_hw_state()
4058 for_each_pipe(dev_priv, pipe) in vlv_wm_get_hw_state()
4060 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, in vlv_wm_get_hw_state()
4061 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); in vlv_wm_get_hw_state()
6289 enum pipe pipe; in g4x_disable_trickle_feed() local
6291 for_each_pipe(dev_priv, pipe) { in g4x_disable_trickle_feed()
6292 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
6293 I915_READ(DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
6296 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); in g4x_disable_trickle_feed()
6297 POSTING_READ(DSPSURF(pipe)); in g4x_disable_trickle_feed()
6392 int pipe; in cpt_init_clock_gating() local
6408 for_each_pipe(dev_priv, pipe) { in cpt_init_clock_gating()
6409 val = I915_READ(TRANS_CHICKEN2(pipe)); in cpt_init_clock_gating()
6417 I915_WRITE(TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
6420 for_each_pipe(dev_priv, pipe) { in cpt_init_clock_gating()
6421 I915_WRITE(TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
6586 enum pipe pipe; in broadwell_init_clock_gating() local
6599 for_each_pipe(dev_priv, pipe) { in broadwell_init_clock_gating()
6600 I915_WRITE(CHICKEN_PIPESL_1(pipe), in broadwell_init_clock_gating()
6601 I915_READ(CHICKEN_PIPESL_1(pipe)) | in broadwell_init_clock_gating()