Lines Matching refs:min_freq
4424 WARN_ON(val < dev_priv->rps.min_freq); in gen6_set_rps()
4463 WARN_ON(val < dev_priv->rps.min_freq); in valleyview_set_rps()
4682 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
4687 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
4702 dev_priv->rps.min_freq, in gen6_init_rps_frequencies()
4711 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4716 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
4729 dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
5032 int min_freq = 15; in __gen6_update_ring_freq() local
5062 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; in __gen6_update_ring_freq()
5065 min_gpu_freq = dev_priv->rps.min_freq; in __gen6_update_ring_freq()
5099 if (gpu_freq < min_freq) in __gen6_update_ring_freq()
5355 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); in valleyview_init_gt_powersave()
5357 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in valleyview_init_gt_powersave()
5358 dev_priv->rps.min_freq); in valleyview_init_gt_powersave()
5360 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
5367 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
5412 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; in cherryview_init_gt_powersave()
5414 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in cherryview_init_gt_powersave()
5415 dev_priv->rps.min_freq); in cherryview_init_gt_powersave()
5420 dev_priv->rps.min_freq) & 1, in cherryview_init_gt_powersave()
5423 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
5430 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
6216 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()
6219 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()