931 				     int level)  in vlv_compute_wm_level()  argument
936 	if (dev_priv->wm.pri_latency[level] == 0)  in vlv_compute_wm_level()
959 				    dev_priv->wm.pri_latency[level] * 10);  in vlv_compute_wm_level()
1035 	int level;  in vlv_invert_wms()  local
1037 	for (level = 0; level < wm_state->num_levels; level++) {  in vlv_invert_wms()
1042 		wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;  in vlv_invert_wms()
1043 		wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;  in vlv_invert_wms()
1049 				wm_state->wm[level].cursor = plane->wm.fifo_size -  in vlv_invert_wms()
1050 					wm_state->wm[level].cursor;  in vlv_invert_wms()
1053 				wm_state->wm[level].primary = plane->wm.fifo_size -  in vlv_invert_wms()
1054 					wm_state->wm[level].primary;  in vlv_invert_wms()
1058 				wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -  in vlv_invert_wms()
1059 					wm_state->wm[level].sprite[sprite];  in vlv_invert_wms()
1072 	int level;  in vlv_compute_wm()  local
1087 		for (level = 0; level < wm_state->num_levels; level++) {  in vlv_compute_wm()
1088 			wm_state->sr[level].plane = sr_fifo_size;  in vlv_compute_wm()
1089 			wm_state->sr[level].cursor = 63;  in vlv_compute_wm()
1101 		for (level = 0; level < wm_state->num_levels; level++) {  in vlv_compute_wm()
1102 			int wm = vlv_compute_wm_level(plane, crtc, state, level);  in vlv_compute_wm()
1106 			if (WARN_ON(level == 0 && wm > max_wm))  in vlv_compute_wm()
1115 				wm_state->wm[level].cursor = wm;  in vlv_compute_wm()
1118 				wm_state->wm[level].primary = wm;  in vlv_compute_wm()
1122 				wm_state->wm[level].sprite[sprite] = wm;  in vlv_compute_wm()
1127 		wm_state->num_levels = level;  in vlv_compute_wm()
1134 			int sprite, level;  in vlv_compute_wm()  local
1136 			for (level = 0; level < wm_state->num_levels; level++)  in vlv_compute_wm()
1137 				wm_state->sr[level].cursor =  in vlv_compute_wm()
1138 					wm_state->wm[level].cursor;  in vlv_compute_wm()
1141 			for (level = 0; level < wm_state->num_levels; level++)  in vlv_compute_wm()
1142 				wm_state->sr[level].plane =  in vlv_compute_wm()
1143 					min(wm_state->sr[level].plane,  in vlv_compute_wm()
1144 					    wm_state->wm[level].primary);  in vlv_compute_wm()
1148 			for (level = 0; level < wm_state->num_levels; level++)  in vlv_compute_wm()
1149 				wm_state->sr[level].plane =  in vlv_compute_wm()
1150 					min(wm_state->sr[level].plane,  in vlv_compute_wm()
1151 					    wm_state->wm[level].sprite[sprite]);  in vlv_compute_wm()
1157 	for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {  in vlv_compute_wm()
1158 		memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));  in vlv_compute_wm()
1159 		memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));  in vlv_compute_wm()
1261 	wm->level = to_i915(dev)->wm.max_level;  in vlv_merge_wm()
1274 		wm->level = min_t(int, wm->level, wm_state->num_levels - 1);  in vlv_merge_wm()
1281 		wm->level = VLV_WM_LEVEL_PM2;  in vlv_merge_wm()
1290 		wm->pipe[pipe] = wm_state->wm[wm->level];  in vlv_merge_wm()
1292 			wm->sr = wm_state->sr[wm->level];  in vlv_merge_wm()
1318 	if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&  in vlv_update_wm()
1319 	    dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)  in vlv_update_wm()
1322 	if (wm.level < VLV_WM_LEVEL_PM5 &&  in vlv_update_wm()
1323 	    dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)  in vlv_update_wm()
1338 		      wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);  in vlv_update_wm()
1343 	if (wm.level >= VLV_WM_LEVEL_PM5 &&  in vlv_update_wm()
1344 	    dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)  in vlv_update_wm()
1347 	if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&  in vlv_update_wm()
1348 	    dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)  in vlv_update_wm()
1828 					 int level, bool is_sprite)  in ilk_plane_wm_reg_max()  argument
1832 		return level == 0 ? 255 : 2047;  in ilk_plane_wm_reg_max()
1835 		return level == 0 ? 127 : 1023;  in ilk_plane_wm_reg_max()
1838 		return level == 0 ? 127 : 511;  in ilk_plane_wm_reg_max()
1841 		return level == 0 ? 63 : 255;  in ilk_plane_wm_reg_max()
1845 					  int level)  in ilk_cursor_wm_reg_max()  argument
1848 		return level == 0 ? 63 : 255;  in ilk_cursor_wm_reg_max()
1850 		return level == 0 ? 31 : 63;  in ilk_cursor_wm_reg_max()
1863 				     int level,  in ilk_plane_wm_max()  argument
1875 	if (level == 0 || config->num_pipes_active > 1) {  in ilk_plane_wm_max()
1889 		if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {  in ilk_plane_wm_max()
1899 	return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));  in ilk_plane_wm_max()
1904 				      int level,  in ilk_cursor_wm_max()  argument
1908 	if (level > 0 && config->num_pipes_active > 1)  in ilk_cursor_wm_max()
1912 	return ilk_cursor_wm_reg_max(dev, level);  in ilk_cursor_wm_max()
1916 				    int level,  in ilk_compute_wm_maximums()  argument
1921 	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);  in ilk_compute_wm_maximums()
1922 	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);  in ilk_compute_wm_maximums()
1923 	max->cur = ilk_cursor_wm_max(dev, level, config);  in ilk_compute_wm_maximums()
1928 					int level,  in ilk_compute_wm_reg_maximums()  argument
1931 	max->pri = ilk_plane_wm_reg_max(dev, level, false);  in ilk_compute_wm_reg_maximums()
1932 	max->spr = ilk_plane_wm_reg_max(dev, level, true);  in ilk_compute_wm_reg_maximums()
1933 	max->cur = ilk_cursor_wm_reg_max(dev, level);  in ilk_compute_wm_reg_maximums()
1937 static bool ilk_validate_wm_level(int level,  in ilk_validate_wm_level()  argument
1958 	if (level == 0 && !result->enable) {  in ilk_validate_wm_level()
1961 				      level, result->pri_val, max->pri);  in ilk_validate_wm_level()
1964 				      level, result->spr_val, max->spr);  in ilk_validate_wm_level()
1967 				      level, result->cur_val, max->cur);  in ilk_validate_wm_level()
1980 				 int level,  in ilk_compute_wm_level()  argument
1985 	uint16_t pri_latency = dev_priv->wm.pri_latency[level];  in ilk_compute_wm_level()
1986 	uint16_t spr_latency = dev_priv->wm.spr_latency[level];  in ilk_compute_wm_level()
1987 	uint16_t cur_latency = dev_priv->wm.cur_latency[level];  in ilk_compute_wm_level()
1990 	if (level > 0) {  in ilk_compute_wm_level()
2004 							     level);  in ilk_compute_wm_level()
2052 		int level, max_level = ilk_wm_max_level(dev);  in intel_read_wm_latency()  local
2113 		for (level = 1; level <= max_level; level++)  in intel_read_wm_latency()
2114 			if (wm[level] != 0)  in intel_read_wm_latency()
2115 				wm[level] += 2;  in intel_read_wm_latency()
2117 				for (i = level + 1; i <= max_level; i++)  in intel_read_wm_latency()
2184 	int level, max_level = ilk_wm_max_level(dev);  in intel_print_wm_latency()  local
2186 	for (level = 0; level <= max_level; level++) {  in intel_print_wm_latency()
2187 		unsigned int latency = wm[level];  in intel_print_wm_latency()
2191 				  name, level);  in intel_print_wm_latency()
2201 		else if (level > 0)  in intel_print_wm_latency()
2205 			      name, level, wm[level],  in intel_print_wm_latency()
2213 	int level, max_level = ilk_wm_max_level(dev_priv->dev);  in ilk_increase_wm_latency()  local
2219 	for (level = 1; level <= max_level; level++)  in ilk_increase_wm_latency()
2220 		wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));  in ilk_increase_wm_latency()
2305 	int level, max_level = ilk_wm_max_level(dev);  in intel_compute_pipe_wm()  local
2350 	for (level = 1; level <= max_level; level++) {  in intel_compute_pipe_wm()
2353 		ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);  in intel_compute_pipe_wm()
2360 		if (!ilk_validate_wm_level(level, &max, &wm))  in intel_compute_pipe_wm()
2363 		pipe_wm->wm[level] = wm;  in intel_compute_pipe_wm()
2373 			       int level,  in ilk_merge_wm_level()  argument
2382 		const struct intel_wm_level *wm = &active->wm[level];  in ilk_merge_wm_level()
2411 	int level, max_level = ilk_wm_max_level(dev);  in ilk_wm_merge()  local
2423 	for (level = 1; level <= max_level; level++) {  in ilk_wm_merge()
2424 		struct intel_wm_level *wm = &merged->wm[level];  in ilk_wm_merge()
2426 		ilk_merge_wm_level(dev, level, wm);  in ilk_wm_merge()
2428 		if (level > last_enabled_level)  in ilk_wm_merge()
2430 		else if (!ilk_validate_wm_level(level, max, wm))  in ilk_wm_merge()
2432 			last_enabled_level = level - 1;  in ilk_wm_merge()
2453 		for (level = 2; level <= max_level; level++) {  in ilk_wm_merge()
2454 			struct intel_wm_level *wm = &merged->wm[level];  in ilk_wm_merge()
2468 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)  in ilk_wm_lp_latency()  argument
2473 		return 2 * level;  in ilk_wm_lp_latency()
2475 		return dev_priv->wm.pri_latency[level];  in ilk_wm_lp_latency()
2484 	int level, wm_lp;  in ilk_compute_wm_results()  local
2493 		level = ilk_wm_lp_to_level(wm_lp, merged);  in ilk_compute_wm_results()
2495 		r = &merged->wm[level];  in ilk_compute_wm_results()
2502 			(ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |  in ilk_compute_wm_results()
2551 	int level, max_level = ilk_wm_max_level(dev);  in ilk_find_best_result()  local
2554 	for (level = 1; level <= max_level; level++) {  in ilk_find_best_result()
2555 		if (r1->wm[level].enable)  in ilk_find_best_result()
2556 			level1 = level;  in ilk_find_best_result()
2557 		if (r2->wm[level].enable)  in ilk_find_best_result()
2558 			level2 = level;  in ilk_find_best_result()
3138 				 int level,  in skl_compute_plane_wm()  argument
3142 	uint32_t latency = dev_priv->wm.skl_latency[level];  in skl_compute_plane_wm()
3196 	if (level >= 1 && level <= 7) {  in skl_compute_plane_wm()
3217 				 int level,  in skl_compute_wm_level()  argument
3230 						level,  in skl_compute_wm_level()
3238 						 ddb_blocks, level,  in skl_compute_wm_level()
3279 	int level, max_level = ilk_wm_max_level(dev);  in skl_compute_pipe_wm()  local
3281 	for (level = 0; level <= max_level; level++) {  in skl_compute_pipe_wm()
3283 				     level, intel_num_planes(intel_crtc),  in skl_compute_pipe_wm()
3284 				     &pipe_wm->wm[level]);  in skl_compute_pipe_wm()
3297 	int level, max_level = ilk_wm_max_level(dev);  in skl_compute_wm_results()  local
3302 	for (level = 0; level <= max_level; level++) {  in skl_compute_wm_results()
3306 			temp |= p_wm->wm[level].plane_res_l[i] <<  in skl_compute_wm_results()
3308 			temp |= p_wm->wm[level].plane_res_b[i];  in skl_compute_wm_results()
3309 			if (p_wm->wm[level].plane_en[i])  in skl_compute_wm_results()
3312 			r->plane[pipe][i][level] = temp;  in skl_compute_wm_results()
3317 		temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;  in skl_compute_wm_results()
3318 		temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];  in skl_compute_wm_results()
3320 		if (p_wm->wm[level].plane_en[PLANE_CURSOR])  in skl_compute_wm_results()
3323 		r->plane[pipe][PLANE_CURSOR][level] = temp;  in skl_compute_wm_results()
3365 		int i, level, max_level = ilk_wm_max_level(dev);  in skl_write_wm_values()  local
3373 		for (level = 0; level <= max_level; level++) {  in skl_write_wm_values()
3375 				I915_WRITE(PLANE_WM(pipe, i, level),  in skl_write_wm_values()
3376 					   new->plane[pipe][i][level]);  in skl_write_wm_values()
3377 			I915_WRITE(CUR_WM(pipe, level),  in skl_write_wm_values()
3378 				   new->plane[pipe][PLANE_CURSOR][level]);  in skl_write_wm_values()
3763 				     int level)  in skl_pipe_wm_active_state()  argument
3769 			active->wm[level].plane_en[i] = is_enabled;  in skl_pipe_wm_active_state()
3770 			active->wm[level].plane_res_b[i] =  in skl_pipe_wm_active_state()
3772 			active->wm[level].plane_res_l[i] =  in skl_pipe_wm_active_state()
3776 			active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;  in skl_pipe_wm_active_state()
3777 			active->wm[level].plane_res_b[PLANE_CURSOR] =  in skl_pipe_wm_active_state()
3779 			active->wm[level].plane_res_l[PLANE_CURSOR] =  in skl_pipe_wm_active_state()
3810 	int level, i, max_level;  in skl_pipe_wm_get_hw_state()  local
3817 	for (level = 0; level <= max_level; level++) {  in skl_pipe_wm_get_hw_state()
3819 			hw->plane[pipe][i][level] =  in skl_pipe_wm_get_hw_state()
3820 					I915_READ(PLANE_WM(pipe, i, level));  in skl_pipe_wm_get_hw_state()
3821 		hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));  in skl_pipe_wm_get_hw_state()
3835 	for (level = 0; level <= max_level; level++) {  in skl_pipe_wm_get_hw_state()
3837 			temp = hw->plane[pipe][i][level];  in skl_pipe_wm_get_hw_state()
3839 						false, i, level);  in skl_pipe_wm_get_hw_state()
3841 		temp = hw->plane[pipe][PLANE_CURSOR][level];  in skl_pipe_wm_get_hw_state()
3842 		skl_pipe_wm_active_state(temp, active, false, true, i, level);  in skl_pipe_wm_get_hw_state()
3902 		int level, max_level = ilk_wm_max_level(dev);  in ilk_pipe_wm_get_hw_state()  local
3909 		for (level = 0; level <= max_level; level++)  in ilk_pipe_wm_get_hw_state()
3910 			active->wm[level].enable = true;  in ilk_pipe_wm_get_hw_state()
4022 	wm->level = VLV_WM_LEVEL_PM2;  in vlv_wm_get_hw_state()
4029 			wm->level = VLV_WM_LEVEL_PM5;  in vlv_wm_get_hw_state()
4052 				wm->level = VLV_WM_LEVEL_DDR_DVFS;  in vlv_wm_get_hw_state()
4064 		      wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);  in vlv_wm_get_hw_state()