138 	dev_priv->ips.r_t = dev_priv->mem_freq;  in i915_ironlake_get_mem_freq()
170 		dev_priv->ips.c_m = 0;  in i915_ironlake_get_mem_freq()
172 		dev_priv->ips.c_m = 1;  in i915_ironlake_get_mem_freq()
174 		dev_priv->ips.c_m = 2;  in i915_ironlake_get_mem_freq()
4216 	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */  in ironlake_enable_drps()
4217 	dev_priv->ips.fstart = fstart;  in ironlake_enable_drps()
4219 	dev_priv->ips.max_delay = fstart;  in ironlake_enable_drps()
4220 	dev_priv->ips.min_delay = fmin;  in ironlake_enable_drps()
4221 	dev_priv->ips.cur_delay = fstart;  in ironlake_enable_drps()
4244 	dev_priv->ips.last_count1 = I915_READ(DMIEC) +  in ironlake_enable_drps()
4246 	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);  in ironlake_enable_drps()
4247 	dev_priv->ips.last_count2 = I915_READ(GFXEC);  in ironlake_enable_drps()
4248 	dev_priv->ips.last_time2 = ktime_get_raw_ns();  in ironlake_enable_drps()
4270 	ironlake_set_drps(dev, dev_priv->ips.fstart);  in ironlake_disable_drps()
5666 	diff1 = now - dev_priv->ips.last_time1;  in __i915_chipset_val()
5674 		return dev_priv->ips.chipset_power;  in __i915_chipset_val()
5683 	if (total_count < dev_priv->ips.last_count1) {  in __i915_chipset_val()
5684 		diff = ~0UL - dev_priv->ips.last_count1;  in __i915_chipset_val()
5687 		diff = total_count - dev_priv->ips.last_count1;  in __i915_chipset_val()
5691 		if (cparams[i].i == dev_priv->ips.c_m &&  in __i915_chipset_val()
5692 		    cparams[i].t == dev_priv->ips.r_t) {  in __i915_chipset_val()
5703 	dev_priv->ips.last_count1 = total_count;  in __i915_chipset_val()
5704 	dev_priv->ips.last_time1 = now;  in __i915_chipset_val()
5706 	dev_priv->ips.chipset_power = ret;  in __i915_chipset_val()
5774 	diffms = now - dev_priv->ips.last_time2;  in __i915_update_gfx_val()
5783 	if (count < dev_priv->ips.last_count2) {  in __i915_update_gfx_val()
5784 		diff = ~0UL - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
5787 		diff = count - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
5790 	dev_priv->ips.last_count2 = count;  in __i915_update_gfx_val()
5791 	dev_priv->ips.last_time2 = now;  in __i915_update_gfx_val()
5796 	dev_priv->ips.gfx_power = diff;  in __i915_update_gfx_val()
5840 	corr2 = (corr * dev_priv->ips.corr);  in __i915_gfx_val()
5847 	return dev_priv->ips.gfx_power + state2;  in __i915_gfx_val()
5912 	if (dev_priv->ips.max_delay > dev_priv->ips.fmax)  in i915_gpu_raise()
5913 		dev_priv->ips.max_delay--;  in i915_gpu_raise()
5940 	if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)  in i915_gpu_lower()
5941 		dev_priv->ips.max_delay++;  in i915_gpu_lower()
5995 	dev_priv->ips.max_delay = dev_priv->ips.fstart;  in i915_gpu_turbo_disable()
5997 	if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))  in i915_gpu_turbo_disable()
6113 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);  in intel_init_emon()