Lines Matching refs:cur_freq
4316 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4321 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4323 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4328 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4429 if (val != dev_priv->rps.cur_freq) { in gen6_set_rps()
4453 dev_priv->rps.cur_freq = val; in gen6_set_rps()
4471 if (val != dev_priv->rps.cur_freq) { in valleyview_set_rps()
4477 dev_priv->rps.cur_freq = val; in valleyview_set_rps()
4492 if (dev_priv->rps.cur_freq <= val) in vlv_set_rps_idle()
4509 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); in gen6_rps_busy()
4544 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) in gen6_rps_boost()
4676 dev_priv->rps.cur_freq = 0; in gen6_init_rps_frequencies()
5524 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in cherryview_enable_rps()
5526 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in cherryview_enable_rps()
5527 dev_priv->rps.cur_freq); in cherryview_enable_rps()
5614 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in valleyview_enable_rps()
5616 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in valleyview_enable_rps()
5617 dev_priv->rps.cur_freq); in valleyview_enable_rps()
5820 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); in __i915_gfx_val()