1039 		const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;  in vlv_invert_wms()
1071 	int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;  in vlv_compute_wm()
1819 	if (INTEL_INFO(dev)->gen >= 8)  in ilk_display_fifo_size()
1821 	else if (INTEL_INFO(dev)->gen >= 7)  in ilk_display_fifo_size()
1830 	if (INTEL_INFO(dev)->gen >= 8)  in ilk_plane_wm_reg_max()
1833 	else if (INTEL_INFO(dev)->gen >= 7)  in ilk_plane_wm_reg_max()
1847 	if (INTEL_INFO(dev)->gen >= 7)  in ilk_cursor_wm_reg_max()
1855 	if (INTEL_INFO(dev)->gen >= 8)  in ilk_fbc_wm_reg_max()
1876 		fifo_size /= INTEL_INFO(dev)->num_pipes;  in ilk_plane_wm_max()
1883 		if (INTEL_INFO(dev)->gen <= 6)  in ilk_plane_wm_max()
2132 	} else if (INTEL_INFO(dev)->gen >= 6) {  in intel_read_wm_latency()
2139 	} else if (INTEL_INFO(dev)->gen >= 5) {  in intel_read_wm_latency()
2152 	if (INTEL_INFO(dev)->gen == 5)  in intel_fixup_spr_wm_latency()
2159 	if (INTEL_INFO(dev)->gen == 5)  in intel_fixup_cur_wm_latency()
2170 	if (INTEL_INFO(dev)->gen >= 9)  in ilk_wm_max_level()
2174 	else if (INTEL_INFO(dev)->gen >= 6)  in ilk_wm_max_level()
2329 	if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)  in intel_compute_pipe_wm()
2415 	if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&  in ilk_wm_merge()
2420 	merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;  in ilk_wm_merge()
2509 		if (INTEL_INFO(dev)->gen >= 8)  in ilk_compute_wm_results()
2520 		if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {  in ilk_compute_wm_results()
2726 	if (INTEL_INFO(dev)->gen >= 7) {  in ilk_write_wm_values()
3718 	if (INTEL_INFO(dev)->gen >= 7 &&  in ilk_update_wm()
4081 	if (INTEL_INFO(dev)->gen >= 7) {  in ilk_wm_get_hw_state()
4637 	if (INTEL_INFO(dev)->gen < 6)  in sanitize_rc6_option()
5084 		} else if (INTEL_INFO(dev)->gen >= 8) {  in __gen6_update_ring_freq()
5133 	switch (INTEL_INFO(dev)->eu_total) {  in cherryview_rps_max_freq()
5716 	if (INTEL_INFO(dev)->gen != 5)  in i915_chipset_val()
5760 	if (INTEL_INFO(dev)->is_mobile)  in pvid_to_extvid()
5803 	if (INTEL_INFO(dev)->gen != 5)  in i915_update_gfx_val()
5855 	if (INTEL_INFO(dev)->gen != 5)  in i915_gfx_val()
6155 	if (INTEL_INFO(dev)->gen < 6)  in intel_suspend_gt_powersave()
6170 	} else if (INTEL_INFO(dev)->gen >= 6) {  in intel_disable_gt_powersave()
6174 		if (INTEL_INFO(dev)->gen >= 9)  in intel_disable_gt_powersave()
6203 	} else if (INTEL_INFO(dev)->gen >= 9) {  in intel_gen6_powersave_work()
6244 	} else if (INTEL_INFO(dev)->gen >= 6) {  in intel_enable_gt_powersave()
6267 	if (INTEL_INFO(dev)->gen < 6)  in intel_reset_gt_powersave()
7061 	if (INTEL_INFO(dev)->gen >= 9) {  in intel_init_pm()
7091 		else if (INTEL_INFO(dev)->gen == 8)  in intel_init_pm()
7135 		if (INTEL_INFO(dev)->num_pipes == 1) {  in intel_init_pm()
7311 	if (req == NULL || INTEL_INFO(dev)->gen < 6)  in intel_queue_rps_boost_for_request()