52 		       int mode, uint8_t write_byte,
53 		       uint8_t *read_byte);
59 			    uint8_t write_byte, uint8_t *read_byte)  in i2c_algo_dp_aux_transaction()
259 	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
263 	uint8_t link_bw;
264 	uint8_t lane_count;
265 	uint8_t dpcd[4];
269 	uint8_t	train_set[4];
270 	uint8_t link_status[DP_LINK_STATUS_SIZE];
358 cdv_intel_dp_link_clock(uint8_t link_bw)  in cdv_intel_dp_link_clock()
545 pack_aux(uint8_t *src, int src_bytes)  in pack_aux()
558 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)  in unpack_aux()
569 		uint8_t *send, int send_bytes,  in cdv_intel_dp_aux_ch()
570 		uint8_t *recv, int recv_size)  in cdv_intel_dp_aux_ch()
671 			  uint16_t address, uint8_t *send, int send_bytes)  in cdv_intel_dp_aux_native_write()
674 	uint8_t	msg[20];  in cdv_intel_dp_aux_native_write()
676 	uint8_t	ack;  in cdv_intel_dp_aux_native_write()
704 			    uint16_t address, uint8_t byte)  in cdv_intel_dp_aux_native_write_1()
712 			 uint16_t address, uint8_t *recv, int recv_bytes)  in cdv_intel_dp_aux_native_read()
714 	uint8_t msg[4];  in cdv_intel_dp_aux_native_read()
716 	uint8_t reply[20];  in cdv_intel_dp_aux_native_read()
718 	uint8_t ack;  in cdv_intel_dp_aux_native_read()
750 		    uint8_t write_byte, uint8_t *read_byte)  in cdv_intel_dp_i2c_aux_ch()
758 	uint8_t msg[5];  in cdv_intel_dp_i2c_aux_ch()
759 	uint8_t reply[2];  in cdv_intel_dp_i2c_aux_ch()
1207 			       uint8_t *recv, int recv_bytes)  in cdv_intel_dp_aux_native_read_retry()
1240 static uint8_t
1241 cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],  in cdv_intel_dp_link_status()
1247 static uint8_t
1248 cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],  in cdv_intel_get_adjust_request_voltage()
1255 	uint8_t l = cdv_intel_dp_link_status(link_status, i);  in cdv_intel_get_adjust_request_voltage()
1260 static uint8_t
1261 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],  in cdv_intel_get_adjust_request_pre_emphasis()
1268 	uint8_t l = cdv_intel_dp_link_status(link_status, i);  in cdv_intel_get_adjust_request_pre_emphasis()
1308 	uint8_t v = 0;  in cdv_intel_get_adjust_train()
1309 	uint8_t p = 0;  in cdv_intel_get_adjust_train()
1313 		uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);  in cdv_intel_get_adjust_train()
1314 		uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);  in cdv_intel_get_adjust_train()
1333 static uint8_t
1334 cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],  in cdv_intel_get_lane_status()
1339 	uint8_t l = cdv_intel_dp_link_status(link_status, i);  in cdv_intel_get_lane_status()
1346 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)  in cdv_intel_clock_recovery_ok()
1349 	uint8_t lane_status;  in cdv_intel_clock_recovery_ok()
1367 	uint8_t lane_align;  in cdv_intel_channel_eq_ok()
1368 	uint8_t lane_status;  in cdv_intel_channel_eq_ok()
1386 			uint8_t dp_train_pat)  in cdv_intel_dp_set_link_train()
1412 			uint8_t dp_train_pat)  in cdv_intel_dplink_set_level()
1432 cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level)  in cdv_intel_dp_set_vswing_premph()
1503 	uint8_t voltage;  in cdv_intel_dp_start_link_train()