382 	u32 pp;  in cdv_intel_edp_panel_vdd_on()  local
390 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_vdd_on()
392 	pp |= EDP_FORCE_VDD;  in cdv_intel_edp_panel_vdd_on()
393 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_vdd_on()
401 	u32 pp;  in cdv_intel_edp_panel_vdd_off()  local
404 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_vdd_off()
406 	pp &= ~EDP_FORCE_VDD;  in cdv_intel_edp_panel_vdd_off()
407 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_vdd_off()
417 	u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;  in cdv_intel_edp_panel_on()  local
423 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_on()
424 	pp &= ~PANEL_UNLOCK_MASK;  in cdv_intel_edp_panel_on()
426 	pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON);  in cdv_intel_edp_panel_on()
427 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_on()
443 	u32 pp, idle_off_mask = PP_ON ;  in cdv_intel_edp_panel_off()  local
448 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_panel_off()
450 	if ((pp & POWER_TARGET_ON) == 0)   in cdv_intel_edp_panel_off()
454 	pp &= ~PANEL_UNLOCK_MASK;  in cdv_intel_edp_panel_off()
457 	pp &= ~POWER_TARGET_ON;  in cdv_intel_edp_panel_off()
458 	pp &= ~EDP_FORCE_VDD;  in cdv_intel_edp_panel_off()
459 	pp &= ~EDP_BLC_ENABLE;  in cdv_intel_edp_panel_off()
460 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_off()
475 	u32 pp;  in cdv_intel_edp_backlight_on()  local
485 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_backlight_on()
487 	pp |= EDP_BLC_ENABLE;  in cdv_intel_edp_backlight_on()
488 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_backlight_on()
496 	u32 pp;  in cdv_intel_edp_backlight_off()  local
501 	pp = REG_READ(PP_CONTROL);  in cdv_intel_edp_backlight_off()
503 	pp &= ~EDP_BLC_ENABLE;  in cdv_intel_edp_backlight_off()
504 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_backlight_off()