Lines Matching refs:m_n
973 struct cdv_intel_dp_m_n *m_n) in cdv_intel_dp_compute_m_n() argument
975 m_n->tu = 64; in cdv_intel_dp_compute_m_n()
976 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3; in cdv_intel_dp_compute_m_n()
977 m_n->gmch_n = link_clock * nlanes; in cdv_intel_dp_compute_m_n()
978 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); in cdv_intel_dp_compute_m_n()
979 m_n->link_m = pixel_clock; in cdv_intel_dp_compute_m_n()
980 m_n->link_n = link_clock; in cdv_intel_dp_compute_m_n()
981 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n); in cdv_intel_dp_compute_m_n()
994 struct cdv_intel_dp_m_n m_n; in cdv_intel_dp_set_m_n() local
1025 mode->clock, adjusted_mode->clock, &m_n); in cdv_intel_dp_set_m_n()
1029 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | in cdv_intel_dp_set_m_n()
1030 m_n.gmch_m); in cdv_intel_dp_set_m_n()
1031 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); in cdv_intel_dp_set_m_n()
1032 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); in cdv_intel_dp_set_m_n()
1033 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); in cdv_intel_dp_set_m_n()