325 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_max_lane_count()  local
328 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {  in cdv_intel_dp_max_lane_count()
329 		max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;  in cdv_intel_dp_max_lane_count()
343 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_max_link_bw()  local
344 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];  in cdv_intel_dp_max_link_bw()
381 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_panel_vdd_on()  local
384 	if (intel_dp->panel_on) {  in cdv_intel_edp_panel_vdd_on()
395 	msleep(intel_dp->panel_power_up_delay);  in cdv_intel_edp_panel_vdd_on()
416 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_panel_on()  local
419 	if (intel_dp->panel_on)  in cdv_intel_edp_panel_on()
432 		intel_dp->panel_on = false;  in cdv_intel_edp_panel_on()
434 		intel_dp->panel_on = true;	  in cdv_intel_edp_panel_on()
435 	msleep(intel_dp->panel_power_up_delay);  in cdv_intel_edp_panel_on()
444 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_panel_off()  local
453 	intel_dp->panel_on = false;  in cdv_intel_edp_panel_off()
468 	msleep(intel_dp->panel_power_cycle_delay);  in cdv_intel_edp_panel_off()
495 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_backlight_off()  local
505 	msleep(intel_dp->backlight_off_delay);  in cdv_intel_edp_backlight_off()
513 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_mode_valid()  local
518 	if (is_edp(encoder) && intel_dp->panel_fixed_mode) {  in cdv_intel_dp_mode_valid()
519 		if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)  in cdv_intel_dp_mode_valid()
521 		if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)  in cdv_intel_dp_mode_valid()
572 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_aux_ch()  local
573 	uint32_t output_reg = intel_dp->output_reg;  in cdv_intel_dp_aux_ch()
753 	struct cdv_intel_dp *intel_dp = container_of(adapter,  in cdv_intel_dp_i2c_aux_ch()  local
756 	struct gma_encoder *encoder = intel_dp->encoder;  in cdv_intel_dp_i2c_aux_ch()
849 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_i2c_init()  local
854 	intel_dp->algo.running = false;  in cdv_intel_dp_i2c_init()
855 	intel_dp->algo.address = 0;  in cdv_intel_dp_i2c_init()
856 	intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;  in cdv_intel_dp_i2c_init()
858 	memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));  in cdv_intel_dp_i2c_init()
859 	intel_dp->adapter.owner = THIS_MODULE;  in cdv_intel_dp_i2c_init()
860 	intel_dp->adapter.class = I2C_CLASS_DDC;  in cdv_intel_dp_i2c_init()
861 	strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);  in cdv_intel_dp_i2c_init()
862 	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';  in cdv_intel_dp_i2c_init()
863 	intel_dp->adapter.algo_data = &intel_dp->algo;  in cdv_intel_dp_i2c_init()
864 	intel_dp->adapter.dev.parent = connector->base.kdev;  in cdv_intel_dp_i2c_init()
868 	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);  in cdv_intel_dp_i2c_init()
899 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_mode_fixup()  local
907 	if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {  in cdv_intel_dp_mode_fixup()
908 		cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);  in cdv_intel_dp_mode_fixup()
909 		refclock = intel_dp->panel_fixed_mode->clock;  in cdv_intel_dp_mode_fixup()
918 				intel_dp->link_bw = bws[clock];  in cdv_intel_dp_mode_fixup()
919 				intel_dp->lane_count = lane_count;  in cdv_intel_dp_mode_fixup()
920 				adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);  in cdv_intel_dp_mode_fixup()
923 				       intel_dp->link_bw, intel_dp->lane_count,  in cdv_intel_dp_mode_fixup()
931 		intel_dp->lane_count = max_lane_count;  in cdv_intel_dp_mode_fixup()
932 		intel_dp->link_bw = bws[max_clock];  in cdv_intel_dp_mode_fixup()
933 		adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);  in cdv_intel_dp_mode_fixup()
936 			      intel_dp->link_bw, intel_dp->lane_count,  in cdv_intel_dp_mode_fixup()
1002 		struct cdv_intel_dp *intel_dp;  in cdv_intel_dp_set_m_n()  local
1008 		intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_set_m_n()
1010 			lane_count = intel_dp->lane_count;  in cdv_intel_dp_set_m_n()
1013 			lane_count = intel_dp->lane_count;  in cdv_intel_dp_set_m_n()
1044 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_mode_set()  local
1047 	intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in cdv_intel_dp_mode_set()
1048 	intel_dp->DP |= intel_dp->color_range;  in cdv_intel_dp_mode_set()
1051 		intel_dp->DP |= DP_SYNC_HS_HIGH;  in cdv_intel_dp_mode_set()
1053 		intel_dp->DP |= DP_SYNC_VS_HIGH;  in cdv_intel_dp_mode_set()
1055 	intel_dp->DP |= DP_LINK_TRAIN_OFF;  in cdv_intel_dp_mode_set()
1057 	switch (intel_dp->lane_count) {  in cdv_intel_dp_mode_set()
1059 		intel_dp->DP |= DP_PORT_WIDTH_1;  in cdv_intel_dp_mode_set()
1062 		intel_dp->DP |= DP_PORT_WIDTH_2;  in cdv_intel_dp_mode_set()
1065 		intel_dp->DP |= DP_PORT_WIDTH_4;  in cdv_intel_dp_mode_set()
1068 	if (intel_dp->has_audio)  in cdv_intel_dp_mode_set()
1069 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;  in cdv_intel_dp_mode_set()
1071 	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);  in cdv_intel_dp_mode_set()
1072 	intel_dp->link_configuration[0] = intel_dp->link_bw;  in cdv_intel_dp_mode_set()
1073 	intel_dp->link_configuration[1] = intel_dp->lane_count;  in cdv_intel_dp_mode_set()
1078 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&  in cdv_intel_dp_mode_set()
1079 	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {  in cdv_intel_dp_mode_set()
1080 		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;  in cdv_intel_dp_mode_set()
1081 		intel_dp->DP |= DP_ENHANCED_FRAMING;  in cdv_intel_dp_mode_set()
1086 		intel_dp->DP |= DP_PIPEB_SELECT;  in cdv_intel_dp_mode_set()
1088 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1089 	DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);  in cdv_intel_dp_mode_set()
1110 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_sink_dpms()  local
1114 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in cdv_intel_dp_sink_dpms()
1172 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_dpms()  local
1174 	uint32_t dp_reg = REG_READ(intel_dp->output_reg);  in cdv_intel_dp_dpms()
1233 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_get_link_status()  local
1236 					      intel_dp->link_status,  in cdv_intel_dp_get_link_status()
1307 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_get_adjust_train()  local
1312 	for (lane = 0; lane < intel_dp->lane_count; lane++) {  in cdv_intel_get_adjust_train()
1313 		uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);  in cdv_intel_get_adjust_train()
1314 		uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);  in cdv_intel_get_adjust_train()
1329 		intel_dp->train_set[lane] = v | p;  in cdv_intel_get_adjust_train()
1366 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_channel_eq_ok()  local
1371 	lane_align = cdv_intel_dp_link_status(intel_dp->link_status,  in cdv_intel_channel_eq_ok()
1375 	for (lane = 0; lane < intel_dp->lane_count; lane++) {  in cdv_intel_channel_eq_ok()
1376 		lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);  in cdv_intel_channel_eq_ok()
1391 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_set_link_train()  local
1393 	REG_WRITE(intel_dp->output_reg, dp_reg_value);  in cdv_intel_dp_set_link_train()
1394 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_set_link_train()
1416 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dplink_set_level()  local
1420 					intel_dp->train_set,  in cdv_intel_dplink_set_level()
1421 					intel_dp->lane_count);  in cdv_intel_dplink_set_level()
1423 	if (ret != intel_dp->lane_count) {  in cdv_intel_dplink_set_level()
1425 				intel_dp->train_set[0], intel_dp->lane_count);  in cdv_intel_dplink_set_level()
1435 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_set_vswing_premph()  local
1439 	if (intel_dp->output_reg == DP_B)  in cdv_intel_dp_set_vswing_premph()
1501 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_start_link_train()  local
1507 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_start_link_train()
1515 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_start_link_train()
1516 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_start_link_train()
1522 				  intel_dp->link_configuration,  in cdv_intel_dp_start_link_train()
1525 	memset(intel_dp->train_set, 0, 4);  in cdv_intel_dp_start_link_train()
1537 				intel_dp->train_set[0],  in cdv_intel_dp_start_link_train()
1538 				intel_dp->link_configuration[0],  in cdv_intel_dp_start_link_train()
1539 				intel_dp->link_configuration[1]);  in cdv_intel_dp_start_link_train()
1544 		cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);  in cdv_intel_dp_start_link_train()
1554 				intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],  in cdv_intel_dp_start_link_train()
1555 				intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);  in cdv_intel_dp_start_link_train()
1557 		if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {  in cdv_intel_dp_start_link_train()
1564 		for (i = 0; i < intel_dp->lane_count; i++)  in cdv_intel_dp_start_link_train()
1565 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in cdv_intel_dp_start_link_train()
1567 		if (i == intel_dp->lane_count)  in cdv_intel_dp_start_link_train()
1571 		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in cdv_intel_dp_start_link_train()
1577 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in cdv_intel_dp_start_link_train()
1585 		DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);  in cdv_intel_dp_start_link_train()
1588 	intel_dp->DP = DP;  in cdv_intel_dp_start_link_train()
1595 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_complete_link_train()  local
1599 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_complete_link_train()
1612 				intel_dp->train_set[0],  in cdv_intel_dp_complete_link_train()
1613 				intel_dp->link_configuration[0],  in cdv_intel_dp_complete_link_train()
1614 				intel_dp->link_configuration[1]);  in cdv_intel_dp_complete_link_train()
1629 		cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);  in cdv_intel_dp_complete_link_train()
1638 				intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],  in cdv_intel_dp_complete_link_train()
1639 				intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);  in cdv_intel_dp_complete_link_train()
1642 		if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {  in cdv_intel_dp_complete_link_train()
1671 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_complete_link_train()
1672 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_complete_link_train()
1681 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_link_down()  local
1682 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_link_down()
1684 	if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)  in cdv_intel_dp_link_down()
1692 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1694 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1698 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()
1699 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1704 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_dp_detect()  local
1708 	if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,  in cdv_dp_detect()
1709 				     sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))  in cdv_dp_detect()
1711 		if (intel_dp->dpcd[DP_DPCD_REV] != 0)  in cdv_dp_detect()
1716 			intel_dp->dpcd[0], intel_dp->dpcd[1],  in cdv_dp_detect()
1717 			intel_dp->dpcd[2], intel_dp->dpcd[3]);  in cdv_dp_detect()
1731 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_detect()  local
1736 	intel_dp->has_audio = false;  in cdv_intel_dp_detect()
1747 	if (intel_dp->force_audio) {  in cdv_intel_dp_detect()
1748 		intel_dp->has_audio = intel_dp->force_audio > 0;  in cdv_intel_dp_detect()
1750 		edid = drm_get_edid(connector, &intel_dp->adapter);  in cdv_intel_dp_detect()
1752 			intel_dp->has_audio = drm_detect_monitor_audio(edid);  in cdv_intel_dp_detect()
1765 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_get_modes()  local
1771 	edid = drm_get_edid(connector, &intel_dp->adapter);  in cdv_intel_dp_get_modes()
1784 			if (edp && !intel_dp->panel_fixed_mode) {  in cdv_intel_dp_get_modes()
1789 						intel_dp->panel_fixed_mode =  in cdv_intel_dp_get_modes()
1798 		if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {  in cdv_intel_dp_get_modes()
1799 			intel_dp->panel_fixed_mode =  in cdv_intel_dp_get_modes()
1801 			if (intel_dp->panel_fixed_mode) {  in cdv_intel_dp_get_modes()
1802 				intel_dp->panel_fixed_mode->type |=  in cdv_intel_dp_get_modes()
1806 		if (intel_dp->panel_fixed_mode != NULL) {  in cdv_intel_dp_get_modes()
1808 			mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);  in cdv_intel_dp_get_modes()
1821 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_detect_audio()  local
1829 	edid = drm_get_edid(connector, &intel_dp->adapter);  in cdv_intel_dp_detect_audio()
1847 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_set_property()  local
1858 		if (i == intel_dp->force_audio)  in cdv_intel_dp_set_property()
1861 		intel_dp->force_audio = i;  in cdv_intel_dp_set_property()
1868 		if (has_audio == intel_dp->has_audio)  in cdv_intel_dp_set_property()
1871 		intel_dp->has_audio = has_audio;  in cdv_intel_dp_set_property()
1876 		if (val == !!intel_dp->color_range)  in cdv_intel_dp_set_property()
1879 		intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;  in cdv_intel_dp_set_property()
1900 	struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;  in cdv_intel_dp_destroy()  local
1904 		if (intel_dp->panel_fixed_mode) {  in cdv_intel_dp_destroy()
1905 			kfree(intel_dp->panel_fixed_mode);  in cdv_intel_dp_destroy()
1906 			intel_dp->panel_fixed_mode = NULL;  in cdv_intel_dp_destroy()
1909 	i2c_del_adapter(&intel_dp->adapter);  in cdv_intel_dp_destroy()
2002 	struct cdv_intel_dp *intel_dp;  in cdv_intel_dp_init()  local
2012 	intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);  in cdv_intel_dp_init()
2013 	if (!intel_dp)  in cdv_intel_dp_init()
2033 	gma_encoder->dev_priv=intel_dp;  in cdv_intel_dp_init()
2034 	intel_dp->encoder = gma_encoder;  in cdv_intel_dp_init()
2035 	intel_dp->output_reg = output_reg;  in cdv_intel_dp_init()
2104 		intel_dp->panel_power_up_delay = cur.t1_t3 / 10;  in cdv_intel_dp_init()
2105                 intel_dp->backlight_on_delay = cur.t8 / 10;  in cdv_intel_dp_init()
2106                 intel_dp->backlight_off_delay = cur.t9 / 10;  in cdv_intel_dp_init()
2107                 intel_dp->panel_power_down_delay = cur.t10 / 10;  in cdv_intel_dp_init()
2108                 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;  in cdv_intel_dp_init()
2111                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,  in cdv_intel_dp_init()
2112                               intel_dp->panel_power_cycle_delay);  in cdv_intel_dp_init()
2115                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);  in cdv_intel_dp_init()
2120 					       intel_dp->dpcd,  in cdv_intel_dp_init()
2121 					       sizeof(intel_dp->dpcd));  in cdv_intel_dp_init()
2131 				intel_dp->dpcd[0], intel_dp->dpcd[1],   in cdv_intel_dp_init()
2132 				intel_dp->dpcd[2], intel_dp->dpcd[3]);  in cdv_intel_dp_init()