49 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);
58 static void cz_ih_enable_interrupts(struct amdgpu_device *adev)  in cz_ih_enable_interrupts()  argument
67 	adev->irq.ih.enabled = true;  in cz_ih_enable_interrupts()
77 static void cz_ih_disable_interrupts(struct amdgpu_device *adev)  in cz_ih_disable_interrupts()  argument
89 	adev->irq.ih.enabled = false;  in cz_ih_disable_interrupts()
90 	adev->irq.ih.rptr = 0;  in cz_ih_disable_interrupts()
104 static int cz_ih_irq_init(struct amdgpu_device *adev)  in cz_ih_irq_init()  argument
112 	cz_ih_disable_interrupts(adev);  in cz_ih_irq_init()
115 	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);  in cz_ih_irq_init()
126 	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);  in cz_ih_irq_init()
128 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in cz_ih_irq_init()
137 	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);  in cz_ih_irq_init()
151 	if (adev->irq.msi_enabled)  in cz_ih_irq_init()
155 	pci_set_master(adev->pdev);  in cz_ih_irq_init()
158 	cz_ih_enable_interrupts(adev);  in cz_ih_irq_init()
170 static void cz_ih_irq_disable(struct amdgpu_device *adev)  in cz_ih_irq_disable()  argument
172 	cz_ih_disable_interrupts(adev);  in cz_ih_irq_disable()
189 static u32 cz_ih_get_wptr(struct amdgpu_device *adev)  in cz_ih_get_wptr()  argument
193 	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);  in cz_ih_get_wptr()
201 		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",  in cz_ih_get_wptr()
202 			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);  in cz_ih_get_wptr()
203 		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;  in cz_ih_get_wptr()
208 	return (wptr & adev->irq.ih.ptr_mask);  in cz_ih_get_wptr()
219 static void cz_ih_decode_iv(struct amdgpu_device *adev,  in cz_ih_decode_iv()  argument
223 	u32 ring_index = adev->irq.ih.rptr >> 2;  in cz_ih_decode_iv()
226 	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);  in cz_ih_decode_iv()
227 	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);  in cz_ih_decode_iv()
228 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);  in cz_ih_decode_iv()
229 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);  in cz_ih_decode_iv()
238 	adev->irq.ih.rptr += 16;  in cz_ih_decode_iv()
248 static void cz_ih_set_rptr(struct amdgpu_device *adev)  in cz_ih_set_rptr()  argument
250 	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);  in cz_ih_set_rptr()
255 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_early_init()  local
257 	cz_ih_set_interrupt_funcs(adev);  in cz_ih_early_init()
264 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_sw_init()  local
266 	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);  in cz_ih_sw_init()
270 	r = amdgpu_irq_init(adev);  in cz_ih_sw_init()
277 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_sw_fini()  local
279 	amdgpu_irq_fini(adev);  in cz_ih_sw_fini()
280 	amdgpu_ih_ring_fini(adev);  in cz_ih_sw_fini()
288 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_hw_init()  local
290 	r = cz_ih_irq_init(adev);  in cz_ih_hw_init()
299 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_hw_fini()  local
301 	cz_ih_irq_disable(adev);  in cz_ih_hw_fini()
308 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_suspend()  local
310 	return cz_ih_hw_fini(adev);  in cz_ih_suspend()
315 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_resume()  local
317 	return cz_ih_hw_init(adev);  in cz_ih_resume()
322 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_is_idle()  local
335 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_wait_for_idle()  local
337 	for (i = 0; i < adev->usec_timeout; i++) {  in cz_ih_wait_for_idle()
349 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_print_status()  local
351 	dev_info(adev->dev, "CZ IH registers\n");  in cz_ih_print_status()
352 	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",  in cz_ih_print_status()
354 	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",  in cz_ih_print_status()
356 	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",  in cz_ih_print_status()
358 	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",  in cz_ih_print_status()
360 	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",  in cz_ih_print_status()
362 	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",  in cz_ih_print_status()
364 	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",  in cz_ih_print_status()
366 	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",  in cz_ih_print_status()
368 	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",  in cz_ih_print_status()
370 	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",  in cz_ih_print_status()
372 	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",  in cz_ih_print_status()
379 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cz_ih_soft_reset()  local
387 		cz_ih_print_status((void *)adev);  in cz_ih_soft_reset()
391 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in cz_ih_soft_reset()
404 		cz_ih_print_status((void *)adev);  in cz_ih_soft_reset()
447 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)  in cz_ih_set_interrupt_funcs()  argument
449 	if (adev->irq.ih_funcs == NULL)  in cz_ih_set_interrupt_funcs()
450 		adev->irq.ih_funcs = &cz_ih_funcs;  in cz_ih_set_interrupt_funcs()