Lines Matching refs:chip
63 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_direction_input() local
70 spin_lock_irqsave(&chip->lock, flags); in pl061_direction_input()
71 gpiodir = readb(chip->base + GPIODIR); in pl061_direction_input()
73 writeb(gpiodir, chip->base + GPIODIR); in pl061_direction_input()
74 spin_unlock_irqrestore(&chip->lock, flags); in pl061_direction_input()
82 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_direction_output() local
89 spin_lock_irqsave(&chip->lock, flags); in pl061_direction_output()
90 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_direction_output()
91 gpiodir = readb(chip->base + GPIODIR); in pl061_direction_output()
93 writeb(gpiodir, chip->base + GPIODIR); in pl061_direction_output()
99 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_direction_output()
100 spin_unlock_irqrestore(&chip->lock, flags); in pl061_direction_output()
107 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_get_value() local
109 return !!readb(chip->base + (BIT(offset + 2))); in pl061_get_value()
114 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_set_value() local
116 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_set_value()
122 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_type() local
142 spin_lock_irqsave(&chip->lock, flags); in pl061_irq_type()
144 gpioiev = readb(chip->base + GPIOIEV); in pl061_irq_type()
145 gpiois = readb(chip->base + GPIOIS); in pl061_irq_type()
146 gpioibe = readb(chip->base + GPIOIBE); in pl061_irq_type()
198 writeb(gpiois, chip->base + GPIOIS); in pl061_irq_type()
199 writeb(gpioibe, chip->base + GPIOIBE); in pl061_irq_type()
200 writeb(gpioiev, chip->base + GPIOIEV); in pl061_irq_type()
202 spin_unlock_irqrestore(&chip->lock, flags); in pl061_irq_type()
212 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_handler() local
217 pending = readb(chip->base + GPIOMIS); in pl061_irq_handler()
230 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_mask() local
234 spin_lock(&chip->lock); in pl061_irq_mask()
235 gpioie = readb(chip->base + GPIOIE) & ~mask; in pl061_irq_mask()
236 writeb(gpioie, chip->base + GPIOIE); in pl061_irq_mask()
237 spin_unlock(&chip->lock); in pl061_irq_mask()
243 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_unmask() local
247 spin_lock(&chip->lock); in pl061_irq_unmask()
248 gpioie = readb(chip->base + GPIOIE) | mask; in pl061_irq_unmask()
249 writeb(gpioie, chip->base + GPIOIE); in pl061_irq_unmask()
250 spin_unlock(&chip->lock); in pl061_irq_unmask()
264 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_ack() local
267 spin_lock(&chip->lock); in pl061_irq_ack()
268 writeb(mask, chip->base + GPIOIC); in pl061_irq_ack()
269 spin_unlock(&chip->lock); in pl061_irq_ack()
284 struct pl061_gpio *chip; in pl061_probe() local
287 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); in pl061_probe()
288 if (chip == NULL) in pl061_probe()
292 chip->gc.base = pdata->gpio_base; in pl061_probe()
299 chip->gc.base = -1; in pl061_probe()
303 chip->base = devm_ioremap_resource(dev, &adev->res); in pl061_probe()
304 if (IS_ERR(chip->base)) in pl061_probe()
305 return PTR_ERR(chip->base); in pl061_probe()
307 spin_lock_init(&chip->lock); in pl061_probe()
309 chip->gc.request = gpiochip_generic_request; in pl061_probe()
310 chip->gc.free = gpiochip_generic_free; in pl061_probe()
313 chip->gc.direction_input = pl061_direction_input; in pl061_probe()
314 chip->gc.direction_output = pl061_direction_output; in pl061_probe()
315 chip->gc.get = pl061_get_value; in pl061_probe()
316 chip->gc.set = pl061_set_value; in pl061_probe()
317 chip->gc.ngpio = PL061_GPIO_NR; in pl061_probe()
318 chip->gc.label = dev_name(dev); in pl061_probe()
319 chip->gc.dev = dev; in pl061_probe()
320 chip->gc.owner = THIS_MODULE; in pl061_probe()
322 ret = gpiochip_add(&chip->gc); in pl061_probe()
329 writeb(0, chip->base + GPIOIE); /* disable irqs */ in pl061_probe()
336 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip, in pl061_probe()
343 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip, in pl061_probe()
349 pl061_direction_output(&chip->gc, i, in pl061_probe()
352 pl061_direction_input(&chip->gc, i); in pl061_probe()
356 amba_set_drvdata(adev, chip); in pl061_probe()
366 struct pl061_gpio *chip = dev_get_drvdata(dev); in pl061_suspend() local
369 chip->csave_regs.gpio_data = 0; in pl061_suspend()
370 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR); in pl061_suspend()
371 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS); in pl061_suspend()
372 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE); in pl061_suspend()
373 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV); in pl061_suspend()
374 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE); in pl061_suspend()
377 if (chip->csave_regs.gpio_dir & (BIT(offset))) in pl061_suspend()
378 chip->csave_regs.gpio_data |= in pl061_suspend()
379 pl061_get_value(&chip->gc, offset) << offset; in pl061_suspend()
387 struct pl061_gpio *chip = dev_get_drvdata(dev); in pl061_resume() local
391 if (chip->csave_regs.gpio_dir & (BIT(offset))) in pl061_resume()
392 pl061_direction_output(&chip->gc, offset, in pl061_resume()
393 chip->csave_regs.gpio_data & in pl061_resume()
396 pl061_direction_input(&chip->gc, offset); in pl061_resume()
399 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS); in pl061_resume()
400 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE); in pl061_resume()
401 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV); in pl061_resume()
402 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE); in pl061_resume()